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Date:   Mon, 10 Sep 2018 18:07:12 +0200 (CEST)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     Anup Patel <anup@brainfault.org>
cc:     Christoph Hellwig <hch@infradead.org>,
        Palmer Dabbelt <palmer@sifive.com>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Atish Patra <atish.patra@wdc.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller
 Driver
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On Mon, 10 Sep 2018, Anup Patel wrote:

> On Mon, Sep 10, 2018 at 7:19 PM, Christoph Hellwig <hch@infradead.org> wrote:
> > On Mon, Sep 10, 2018 at 03:45:42PM +0200, Thomas Gleixner wrote:
> >> > He has an irqchip that is called from the RISC-V exception handler
> >> > when the interrupt flag is set in scause and then dispatches to one
> >> > of:  IPI, timer, actual irqchip.
> >>
> >> So the per cpu timer is the only per cpu interrupt and that thing is used
> >> unconditionally, right?
> >
> > Yes.  external is chained and IPI is still handled explicitly.
> 
> On riscv64, there are 64 local interrupts (i.e. per-CPU interrupts).
> 
> Three of these local interrupts have clearly defined use:
> 1. Software interrupt (inter-processor interrupt)
> 2. External interrupt (interrupt from PLIC)
> 3. Timer interrupt (interrupt from per-CPU timer)
> 
> Other local interrupts are available for future use.
> 
> Taking inspiration from ARM world, I had give quite a few
> examples how these RISC-V local interrupts can be used
> for other purposes:
> 1. per-CPU interrupt for per-HART performance monitoring unit
> 2. interrupt controller virtualizaton extension can use per-CPU
> interrupts for managing resources (just like ARM GICv2/v3 virt
> extensions)
> 3. bus errors can be reported as per-CPU interrupts
> 
> Considering above, it is better to have a distinct irqchip and
> irq_domain for all local interrupts (just like this patch).

If that's the future usage and that's what my impression was, under which I
changed my mind, yes, then having a domain model is certainly of advantage
especially when those things end up being different per SoC.

Thanks,

	tglx