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From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 10 Sep 2018 22:41:22 +0530
Message-ID: <CAAhSdy3AN4YTaAJCR50WMB8CgaoZNeT9uOZt2GH2O6i8Y6z6ew@mail.gmail.com>
Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
To:     Christoph Hellwig <hch@infradead.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Palmer Dabbelt <palmer@sifive.com>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Atish Patra <atish.patra@wdc.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv@lists.infradead.org
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On Mon, Sep 10, 2018 at 10:09 PM, Christoph Hellwig <hch@infradead.org> wrote:
> On Mon, Sep 10, 2018 at 10:05:42PM +0530, Anup Patel wrote:
>> I am quite sure RISC-V spec does not restrict the use of other
>> local interrupts. Different CPU implementations can have their
>> own local interrupts.
>
> Please take a look at sections 3.1.14 and 4.1.1 of the RISC-V privileged
> spec 1.10.

RISC-V priv spec 1.10 defines the 9 bits in MIE and MIP registers and
other bits are reserved.

The unused bits in MIP are WIRI (reserved write ignored and read ignored)
and unused bits in MIE are WPRI (reserved write preserve values and
read ignored).

The RISC-V priv spec 1.10 does not tell that unused reserved bits in
MIE/MIP cannot be used for:
1. CPU implementation specific local interrupts
2. Per-CPU device interrupts.

The RISC-V priv spec 1.10 tries to only describe MIE/MIP bits which
are mandatory on any RISC-V 1.10 compliant CPU but it possible to
used other reserved bits for implementation specific local interrupts.

Regards,
Anup