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Date:   Mon, 10 Sep 2018 20:17:30 +0200
From:   Borislav Petkov <bp@alien8.de>
To:     Pu Wen <puwen@hygon.cn>
Cc:     tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
        x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com,
        linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v6 05/16] perf/x86: Add Hygon Dhyana support to PMU
 infrastructure
Message-ID: <20180910181730.GF4386@zn.tnic>
References: <cover.1536550549.git.puwen@hygon.cn>
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On Mon, Sep 10, 2018 at 09:16:43PM +0800, Pu Wen wrote:
> The PMU architecture for Hygon Dhyana CPU is similar to the AMD Family
> 17h one. To support Hygon Dhyana PMU, call amd_pmu_init() to share
> AMD PMU initialization flow, and change the PMU name to "HYGON".
> 
> The Hygon Dhyana CPU support both legacy and extension PMC MSRs(perf

I don't know but for some reason, you are writing "Hygon Dhyana CPU" as
being plural. But it is singular:

"The Hygon Dhyna CPU supports both ..."
			    ^
			   |||

> counter registers and event selection registers), so add Hygon Dhyana
> support to get bit offset in the similar way as AMD does.

"to get bit offset"?

> Signed-off-by: Pu Wen <puwen@hygon.cn>
> ---
>  arch/x86/events/amd/core.c             |  4 ++++
>  arch/x86/events/amd/uncore.c           | 20 +++++++++++++-------
>  arch/x86/events/core.c                 |  4 ++++
>  arch/x86/kernel/cpu/perfctr-watchdog.c |  2 ++
>  4 files changed, 23 insertions(+), 7 deletions(-)

With that addressed:

Reviewed-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

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