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From:   Pu Wen <puwen@hygon.cn>
Subject: Re: [PATCH v6 05/16] perf/x86: Add Hygon Dhyana support to PMU
 infrastructure
To:     Borislav Petkov <bp@alien8.de>
Cc:     tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
        x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com,
        linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org
References: <cover.1536550549.git.puwen@hygon.cn>
 <1e7b20df2bb5ebca6d72339f8b4e1453325cef10.1536550550.git.puwen@hygon.cn>
 <20180910181730.GF4386@zn.tnic>
Message-ID: <ae6c1c18-f503-2172-279b-5920e7fdb19a@hygon.cn>
Date:   Tue, 11 Sep 2018 15:00:08 +0800
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On 2018/9/11 2:17, Borislav Petkov wrote:
>> The Hygon Dhyana CPU support both legacy and extension PMC MSRs(perf
> 
> I don't know but for some reason, you are writing "Hygon Dhyana CPU" as
> being plural. But it is singular:
> 
> "The Hygon Dhyna CPU supports both ..."
> 			    ^
> 			   |||

Will take more care of the usage between singular and plural and fix
the typo.

>> counter registers and event selection registers), so add Hygon Dhyana
>> support to get bit offset in the similar way as AMD does.
> 
> "to get bit offset"?

These words are used with the tendency to explain what the patch do,
actually they are not needed and will be removed.

-- 
Regards,
Pu Wen