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[209.132.180.67]) by mx.google.com with ESMTP id m24-v6si21244724pfk.56.2018.09.11.06.20.58; Tue, 11 Sep 2018 06:21:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727724AbeIKSS4 (ORCPT + 99 others); Tue, 11 Sep 2018 14:18:56 -0400 Received: from shell.v3.sk ([90.176.6.54]:42259 "EHLO shell.v3.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726689AbeIKSS4 (ORCPT ); Tue, 11 Sep 2018 14:18:56 -0400 Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id A315CB2367; Tue, 11 Sep 2018 15:19:35 +0200 (CEST) Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id JRUEHE8ENPvS; Tue, 11 Sep 2018 15:19:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id C0C21B2669; Tue, 11 Sep 2018 15:19:32 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.v3.sk Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id B1sVBxoqUI6W; Tue, 11 Sep 2018 15:19:32 +0200 (CEST) Received: from belphegor (nat-pool-brq-t.redhat.com [213.175.37.10]) by zimbra.v3.sk (Postfix) with ESMTPSA id D1B47B2367; Tue, 11 Sep 2018 15:19:31 +0200 (CEST) Message-ID: <3ab50e5f4c647229b575bc5de5e80f9ed80ac938.camel@v3.sk> Subject: Re: [PATCH 1/4] dt-bindings: mrvl,mmp-timer: add clock From: Lubomir Rintel To: Rob Herring Cc: "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , devicetree@vger.kernel.org, Daniel Lezcano , Thomas Gleixner , Mark Rutland , Eric Miao , Haojian Zhuang , Russell King Date: Tue, 11 Sep 2018 15:19:30 +0200 In-Reply-To: References: <20180910113031.42634-1-lkundrak@v3.sk> <20180910113031.42634-2-lkundrak@v3.sk> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-1.fc28) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2018-09-10 at 10:21 -0500, Rob Herring wrote: > On Mon, Sep 10, 2018 at 6:30 AM Lubomir Rintel > wrote: > > > > The timer needs the timer clock to be enabled, otherwise it stops > > ticking. > > > > Signed-off-by: Lubomir Rintel > > --- > > Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp- > > timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp- > > timer.txt > > index 9a6e251462e7..a2ede0bd12ca 100644 > > --- a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt > > +++ b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt > > @@ -4,10 +4,12 @@ Required properties: > > - compatible : Should be "mrvl,mmp-timer". > > - reg : Address and length of the register set of timer > > controller. > > - interrupts : Should be the interrupt number. > > +- clocks : Should contain a single entry describing the clock > > input. > > So now pxa910 and pxa168 dts files have errors because they are > missing a required clock. Ah, right. Sorry. Will make it optional then. A brief look at 16x datasheet suggests that the "fast clock" source circuitry needs to be enabled in the PMU, whereas the internal "32.768" might not be. Perhaps the timer clk is always enabled in PMU, or the slow clock is used on those platforms? No idea. > Plus somehow other MMP2 platforms either > worked without a clock or have been broken. I don't have a MMP2 datasheet, but if things work the same as on a 16x, then mach-mmp/time.c indeed chooses the fast timer. The DT MMP2 platform certainly is certainly broken*. Not sure about the BSP-based platforms. * in other ways too: even when the missing clock is worked around with "clk_ignore_unused" the wrong rate gets chosen and the timer runs too slow. (Fix posted recently.) > You can't add new required properties to a binding. That breaks > backward compatibility. Should I make an effort to make the driver look up and enable the clock on MMP2 even if it doesn't find the clock property in DT? It won't work otherwise, which is why I thought I can't break it further (I didn't notice that the same binding and driver are used on PXA168 and PXA910). > Rob Thank you, Lubo > > > > Example: > > timer0: timer@d4014000 { > > compatible = "mrvl,mmp-timer"; > > reg = <0xd4014000 0x100>; > > interrupts = <13>; > > + clocks = <&coreclk 2>; > > }; > > -- > > 2.17.1 > >