Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp3459167imm; Sun, 16 Sep 2018 19:20:14 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ0BK1Ln7zpSvyvM7dPF1a6DWPRVIaJLA7tbHYzZkS56cv89ZHfPmb2AHh2kOd7UvyOE6ti X-Received: by 2002:a17:902:c6:: with SMTP id a64-v6mr22819726pla.180.1537150814700; Sun, 16 Sep 2018 19:20:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537150814; cv=none; d=google.com; s=arc-20160816; b=CldCMndAs8c/jYlwh7+noDsgMzqrlj++YjgG9ZhnAcEtO3mEzPmW8oe8O2k1cMmMoI lSpvTscI5fMqOUEM03lS5e/Zw3sFYHC8sa4S7NAWxxRzrSbkp14iafllTnqcffRLmx/E brWI3PDEGeO5pViu5fUgOuQsDzst6meScZrFaeZDqCKEhRwzwZNczrFOJDtLY0IjTS7K e6YTkiy5+9uVFtIjjS6GZhIx3XrmMzfYU0ftpRF8ZJcf257v2S2yViX0f7iX9VNVgaAI itutY7d0PbllneD7k0e2+40tImiJX7ynrPfqXjHDUtwxFXk6tAJdanpDXQjq9fGeywn/ Vw+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=SCGgjhgstw60GgnS1pfBySxDV8/CAmNd8yqJ7Qx84VM=; b=f0Apoi1+aDePl/f43EXAfXV8cRyJCLp3inALmVqCMGtpvfDHJLz6Hogoay7ZBV9/jd 0545DQrxbTVolIs6sG3mlpHCjGwOuf3KJ9N+XCdQQlscLjBssqX8NoULDQ+7DNtkbRV3 9iGdW6+VPmrdnOSFX8xxv3g3di+R1QKaVF52W9GFDxJ5DpOfbdRrdrzpO1eY5L1ndVAa HTBFouSwCuDa3067k6rC6rOgN7/cdSJRrCdBgejzYuPENFSthGyeXlficD/OKYzXDNnn VmIM1GUmNbAN32AaAdJDp2+8tO8gGSoGO1f7K4D4DkX3dQYISptp2SX6k25dewzQgvUH 2SvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cb1-v6si16224022plb.128.2018.09.16.19.20.00; Sun, 16 Sep 2018 19:20:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728169AbeIQHo4 (ORCPT + 99 others); Mon, 17 Sep 2018 03:44:56 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:9903 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727324AbeIQHoz (ORCPT ); Mon, 17 Sep 2018 03:44:55 -0400 X-UUID: 9cd10923988e44d79f2ce1c6cce5d8d6-20180917 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 923662005; Mon, 17 Sep 2018 10:19:33 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 17 Sep 2018 10:19:31 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 17 Sep 2018 10:19:31 +0800 From: Leilk Liu To: Mark Brown CC: Mark Rutland , Matthias Brugger , Sascha Hauer , , , , , , , Leilk Liu Subject: [PATCH v3 1/3] spis: mediatek: add bindings for Mediatek MT2712 soc platform Date: Mon, 17 Sep 2018 10:19:20 +0800 Message-ID: <1537150762-7072-2-git-send-email-leilk.liu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1537150762-7072-1-git-send-email-leilk.liu@mediatek.com> References: <1537150762-7072-1-git-send-email-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds a DT binding documentation for the MT2712 soc. Signed-off-by: Leilk Liu --- .../devicetree/bindings/spi/spi-slave-mt27xx.txt | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt diff --git a/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt new file mode 100644 index 0000000..09cb2c4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-slave-mt27xx.txt @@ -0,0 +1,32 @@ +Binding for MTK SPI Slave controller + +Required properties: +- compatible: should be one of the following. + - mediatek,mt2712-spi-slave: for mt2712 platforms +- reg: Address and length of the register set for the device. +- interrupts: Should contain spi interrupt. +- clocks: phandles to input clocks. + It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>. +- clock-names: should be "spi" for the clock gate. + +Optional properties: +- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>. +- assigned-clock-parents: parent of mux clock. + It's PLL, and should be on of the following. + - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ. + It's the default one. + - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ. + - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. + - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. + +Example: +- SoC Specific Portion: +spis1: spi@10013000 { + compatible = "mediatek,mt2712-spi-slave"; + reg = <0 0x10013000 0 0x100>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_AO_SPI1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; +}; -- 1.7.9.5