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Date:   Mon, 17 Sep 2018 10:23:36 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Reinette Chatre <reinette.chatre@intel.com>
Cc:     tglx@linutronix.de, fenghua.yu@intel.com, tony.luck@intel.com,
        mingo@redhat.com, acme@kernel.org, gavin.hindman@intel.com,
        jithu.joseph@intel.com, dave.hansen@intel.com, hpa@zytor.com,
        x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 2/6] perf/core: Add helper to obtain performance
 counter index
Message-ID: <20180917082336.GP24124@hirez.programming.kicks-ass.net>
References: <cover.1536685533.git.reinette.chatre@intel.com>
 <6f93048a74c66a275f8eb6e1298f10552d1e5d95.1536685533.git.reinette.chatre@intel.com>
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On Tue, Sep 11, 2018 at 10:14:33AM -0700, Reinette Chatre wrote:
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 53c500f0ca79..c04dc666425c 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -1025,6 +1025,27 @@ static inline int in_software_context(struct perf_event *event)
>  	return event->ctx->pmu->task_ctx_nr == perf_sw_context;
>  }
>  
> +/**
> + * perf_rdpmc_index - Return PMC counter used for event
> + * @event: the perf_event to which the PMC counter was assigned
> + *
> + * The counter assigned to this performance event may change if interrupts
> + * are enabled. This counter should thus never be used while interrupts are
> + * enabled. Before this function is used to obtain the assigned counter the
> + * event could be checked for validity using, for example,
> + * perf_event_read_local(), within the same interrupt disabled section in
> + * which this counter is planned to be used.
> + *
> + * Return: The index of the performance monitoring counter assigned to
> + * @perf_event.
> + */
> +static inline int perf_rdpmc_index(struct perf_event *event)
> +{
> +	lockdep_assert_irqs_disabled();
> +
> +	return event->hw.event_base_rdpmc;
> +}

I said arch/x86/include/asm/perf_events.h and call it:
x86_perf_rdpmc_index().

This function is very much x86 specific.