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From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 17 Sep 2018 21:24:31 +0530
Message-ID: <CAAhSdy3NSNn=YicWdnyos87A7gDq0O1BMvQQ0FVmCtv+rBo=vg@mail.gmail.com>
Subject: Re: [RFC 3/3] RISC-V: Remove per cpu clocksource
To:     Thomas Gleixner <tglx@linutronix.de>
Cc:     Christoph Hellwig <hch@infradead.org>,
        Atish Patra <atish.patra@wdc.com>,
        Palmer Dabbelt <palmer@sifive.com>,
        linux-riscv@lists.infradead.org,
        Mark Rutland <mark.rutland@arm.com>, robh@kernel.org,
        Damien Le Moal <Damien.LeMoal@wdc.com>,
        Marc Zyngier <marc.zyngier@arm.com>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>
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On Mon, Sep 17, 2018 at 8:35 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Mon, 17 Sep 2018, Christoph Hellwig wrote:
> > > Just for the record, this would be the first (architected) timer ever which
> > > just works. I'm having a hard time to believe this, but I'd certainly
> > > welcome it.
> >
> > And that would be the contact with reality.
>
> I've dealt with the reality of timers for a long time ....

I think the problem is we don't have separate DT node
for RISC-V timer. Instead, we have been probing timer
for each CPU DT node.

Ideally, we should have one DT node for RISC-V timer
and the DT should should also describe the local interrupts
to be used for RISC-V timer.

Regards,
Anup