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[209.132.180.67]) by mx.google.com with ESMTP id d31-v6si19187911pla.479.2018.09.18.12.45.02; Tue, 18 Sep 2018 12:45:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OQ642pAl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729705AbeISBRg (ORCPT + 99 others); Tue, 18 Sep 2018 21:17:36 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:45247 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726839AbeISBRf (ORCPT ); Tue, 18 Sep 2018 21:17:35 -0400 Received: by mail-io1-f66.google.com with SMTP id e12-v6so2550007iok.12 for ; Tue, 18 Sep 2018 12:43:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Zp/prRIqX6uqNKhny7UXEwgjhvksawDmeFnFpvf7LwQ=; b=OQ642pAlwGBsrCSFDUTUCQE/65Sb26ekCpkWi8yIuBxJ36nY1eioRaq1eP2vWXzd9a P/R6LoCJBc6wEvoY0ol1V0baabPi3pqUz3ntqmpkljclzarwGTk97/CIzixz4Vgs5Jx0 86K7V0NRKuksPAr2j/tX8reRQ98/Vw5/qRQp4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Zp/prRIqX6uqNKhny7UXEwgjhvksawDmeFnFpvf7LwQ=; b=mdlPUjJ9dPaYEGmr/TvBZbDs2wl+jbiQp0yJCQzKQs5IPgFVBK4V7Nd2U0SVfMNK79 lLH0xbHJFKJuyHa8BI2E7XDsfFuuiq2xkbrMZNDdZQLOhqU5O9i8dnIoCOwawa7hdjKZ LrAbbwlaYhfK547/B9PgELOTBJbfCPkpO8dgXvMtzSH6jMd7ki+ISPG62+2pSDm5ibXY wfEfYCIaNTEff3/pmbTuxQWFgk2W2JNEYFyGDhNnao9LuwCs8pbyR4omjWa46PuXNSal JdepAC6Rby97W48GHCG3GzCCdX3cF8Qym5I6VFpg16Msfs47S1y6+rttSY6o/e/NqFNw TgbQ== X-Gm-Message-State: APzg51By1CCIYebAEUjgy+W2FLcocanlHJe00Q9ltWmqWEIExFLc9CY8 F416U0XX9MBHncQjC5SpB7fDDbAbwSFqpVaSZxXKYQ== X-Received: by 2002:a6b:c3c4:: with SMTP id t187-v6mr26009430iof.304.1537299810400; Tue, 18 Sep 2018 12:43:30 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Tue, 18 Sep 2018 12:43:17 -0700 Message-ID: Subject: Re: [PATCH v2 03/22] pinctrl: mediatek: extend struct mtk_pin_field_calc to pinctrl-mtk-common-v2.c To: Sean Wang Cc: "moderated list:ARM/Mediatek SoC support" , Linux ARM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Ryder Lee Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 8, 2018 at 4:08 AM wrote: > From: Sean Wang > > This patch adds members sz_reg fixed in struct mtk_pin_field_calc > > - The 'fixed' is used to represent the consecutive pins share the same > bits within the same register with the 1st pin so that it can largely > reduce the entry size a bit. > > - The 'sz_reg' is used to indicate the range of bits we use in a register > that may vary by SoC > > The above changes make the code more generic and this is useful as there > might be other existing or future chips all use the same logic to access > their register set and then being a little more abstract could help in the > long run. > > Signed-off-by: Ryder Lee > Signed-off-by: Sean Wang Patch applied. Yours, Linus Walleij