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[209.132.180.67]) by mx.google.com with ESMTP id b9-v6si18547684pfi.99.2018.09.18.12.57.43; Tue, 18 Sep 2018 12:57:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eBpqO+Nm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729942AbeISBbH (ORCPT + 99 others); Tue, 18 Sep 2018 21:31:07 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:52869 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729538AbeISBbG (ORCPT ); Tue, 18 Sep 2018 21:31:06 -0400 Received: by mail-it0-f68.google.com with SMTP id h3-v6so5083756ita.2 for ; Tue, 18 Sep 2018 12:56:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=MmDLZJU+og8oY+kReLl5bOixoOX55wnLybK/AmCVRMA=; b=eBpqO+NmdPCOgvcs3qs1491nfWepbfHVNGWGNVlOguQkbVpux09S/6UggDsVTuPZWf ohiopDs1CUx0UkSmct8EMU8ixPZMyo6J5jcu8Jo2WDJLzax9y7SWSMN6KZ3d60qTAtdc ZJi8hfbDgao+xOJXQsVp1Jiz4UJze7Qj4Azao= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MmDLZJU+og8oY+kReLl5bOixoOX55wnLybK/AmCVRMA=; b=Xv10WsWzvjjKnNPKyhcLsE6Q/LUQHiVaSGL1X+c1tcH4fsmVD5+mvDv/FbzuFHsU+U 4npW95TkgE9eUhQd/hd+U48nTvvKthjZZTJn2KmbuF9DgQObBNywdHDFWrxGC7IYEPIP TxqIwu7101/BNNjiKILmVHyzF9j2hp7oTruaFPpaFN0J1VeRsjho97sAsXB81rxymg/w 7m6rgSiqEArBq6nxpj2kvSNN7j6UCcoayf3KYKsT1hylJZW38DcmtxulG/BTiAQ7Brfp xLrXym/48OYmvw0iCdi0s5owH4JVxe40SZDD+ToJeSJ5sinynOyn9bl6+jJXE3hPAE8N FzuQ== X-Gm-Message-State: APzg51A8Uc2XpRfZwoyubU7GavoFpxHsfXafp9VtWsdneBNVIryGsZus 7EgOoCZZRS9e7ODg56bnBB1OFhwpyRlYg7TbjQAhbg== X-Received: by 2002:a24:7605:: with SMTP id z5-v6mr6782129itb.62.1537300618362; Tue, 18 Sep 2018 12:56:58 -0700 (PDT) MIME-Version: 1.0 References: <8c4a741e7ed695d85844a1a550b956d767661b44.1536404280.git.sean.wang@mediatek.com> In-Reply-To: <8c4a741e7ed695d85844a1a550b956d767661b44.1536404280.git.sean.wang@mediatek.com> From: Linus Walleij Date: Tue, 18 Sep 2018 12:56:45 -0700 Message-ID: Subject: Re: [PATCH v2 14/22] pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c To: Sean Wang Cc: "moderated list:ARM/Mediatek SoC support" , Linux ARM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 8, 2018 at 4:07 AM wrote: > From: Sean Wang > > Certain SoC own multiple register base for accessing each pin groups, > it's easy to be done with extend struct mtk_pin_field_calc to support > the kind of SoC such as MT8183. > > Signed-off-by: Sean Wang Patch applied. Yours, Linus Walleij