Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp1789256imm; Thu, 20 Sep 2018 02:58:37 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbY1JUUc5dF7VOQxUCuG5aKzN2/p8JAkI9fMP0hT8Dh7PEYpIc3wT3y3xflgAxhiIViDmc5 X-Received: by 2002:aa7:88d3:: with SMTP id p19-v6mr40704914pfo.160.1537437517081; Thu, 20 Sep 2018 02:58:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537437517; cv=none; d=google.com; s=arc-20160816; b=MJP75JHF7l3Fbq/YmsqU60btnnmPLiNWm/r1Lwhir7RHATPQevgbvSHLRoc2CnrQ/S AtWd20gDBCC+nptB1vMXt5o1ZXrTLl4CaNyiirLt4pmr4i8xPuBUF5+VkwaFWlXcaERR M/VkLcbU5bWv3TEYYM/C3jKmpNgDArfRGGpHrBmyb5zWwg5BTUFIgQE2Ok3eUv4rGobG KCbKrLNFW6lZVTFnANyEBzKKnnHXoGYzoOV34frJ/VeNpkNXE7D1g5wTc7wa0z0z6jv+ fSwNd5zrv3EYKyiK1/+1lwcETS3CYzHPdjBmNfaqcvMYPhaUquBX/bh+K9l+76RjPc0L 8JFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=mOU2j+9K/GvvlKiclvlbY4aFVqWrQqAmxTdCwc0bScQ=; b=I/tglPhBsc7yF9dMYL6mswIsAabiH1bLwpwnsKgvi+d7UQ3DzJ40xzyptVVNUCD6sn PjbOvZiUCLXTlP3zmvNM3Tk8e75THMbBIiUacdgrs4bGLL4IAS3HW4RD7RtUhhCJGJGR IVEhw+X8j+VPMzJGM2mjbq16es4GuEY5IFH80AB+fU6cem2U4gAMkrqxtBQotpQqMsCm 7QP+EzCiILue08iGeH1r+w0H5UDgqhbsAniToNSi3GIknFc427FmNmoGrWsp9f88aSvo ZQmgRAYI1vF+Ic8EfA8hpf+goyafhp13aeWv0QIDmEfpQvaxhxgiFndELWRUu5gfftPU E1GQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 19-v6si23411485pgy.577.2018.09.20.02.58.21; Thu, 20 Sep 2018 02:58:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732285AbeITPkp (ORCPT + 99 others); Thu, 20 Sep 2018 11:40:45 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:60128 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731025AbeITPkn (ORCPT ); Thu, 20 Sep 2018 11:40:43 -0400 X-UUID: ead11b1fe975401498d670330730039c-20180920 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 348702845; Thu, 20 Sep 2018 17:57:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 20 Sep 2018 17:57:57 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 20 Sep 2018 17:57:57 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v1 2/3] clk: mediatek: update clock driver of MT2712 Date: Thu, 20 Sep 2018 17:57:26 +0800 Message-ID: <20180920095727.11868-4-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5.2.gbdf23ab In-Reply-To: <20180920095727.11868-1-weiyi.lu@mediatek.com> References: <20180920095727.11868-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 20A164BE42AF21DB61E1F1C98006F89DD1A788111F36F08970D9CD6EC76A85122000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to 3rd ECO design change, 1. Add new fixed factor clock of audio. 2. Add the parent clocks for audio clock mux. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mt2712.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 991d4093726e..e36f4aab634d 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = { 4), FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, + 3), }; static const char * const axi_parents[] = { @@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = { "apll1_ck", "apll1_d2", "apll1_d4", - "apll1_d8" + "apll1_d8", + "apll1_d3" }; static const char * const a2sys_hp_parents[] = { @@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = { "apll2_ck", "apll2_d2", "apll2_d4", - "apll2_d8" + "apll2_d8", + "apll2_d3" }; static const char * const asm_l_parents[] = { -- 2.12.5.2.gbdf23ab