Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp1791092imm; Thu, 20 Sep 2018 03:00:47 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZzDhZelsR+FaQ+webhM4QUk8TsrLD3mgzsLCilxhCRRhz9SQmyeWXdSS7WxKLz8xQWTpsr X-Received: by 2002:a17:902:b7c3:: with SMTP id v3-v6mr38618591plz.238.1537437646980; Thu, 20 Sep 2018 03:00:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537437646; cv=none; d=google.com; s=arc-20160816; b=TNB5rLbpVykHv3DCBdaFgV4rCx3IHtFvGmLJnhZEjT0dCTIlMv2Nwzw/vQtYDigg/d yD3zRPH67it1aMzBU8B3V9+mkUcYKMYshSSVAJ+qZmkmAedV6r4tNdE20dGx1jHQ2Ed4 M+GrsG9mmvTnz30zOOoVkIiBkN+QIVZKz0SFqTmGYuEkL6DG/982ZG8GhHU7JQ1cb9nN CxSjnnH7LbnKWSlrXkZq6k8NFkrmJKaTuDLZrq+/ztMF2SuMlX8nnOPOuKOCApuFgsyu ISkzzAFnZHzN2QtEe4OkFlRI7/yhDp3fMICvzn5Km3wffHC13L4PJFLUd4SSWy3lw8Bi zmpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=jdWhm5Ew5+gOlSWtRgwa0AHdITecHAZ0O7lSfBIKs9Y=; b=wAw7KcxmrNlp1m7sf1/MvAlI1gL7b6qqt3GUWoidu4El13ym8iKsk8Ff8psbeE3VYu K+zNMgQFIm+S2vAjDSgz9jJHF55o8FPUZQE8/Xml61bRJr6LSmTdeEYcEUM+x0GbQJsO WsKhUL709l4A6CjOFW788WFztqBsCbWBC8lqLnsKWBCn+P7cb0OPSTgahZwMDKBjzff0 M91IFT7+V0rK+5fZ+4Kcou61ZhzlmUifsddAAe80WuTVDlLQ+n8GiW61nPOWp9Epo+ky YdTOsid2CgApJvRng3jou5cxC5l4qcWSUH3xcJY88VK+yL9nPjQqOpKYUpwIR45tFJxw Pscg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u10-v6si22941021plu.506.2018.09.20.03.00.30; Thu, 20 Sep 2018 03:00:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731756AbeITPkm (ORCPT + 99 others); Thu, 20 Sep 2018 11:40:42 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7295 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727633AbeITPkm (ORCPT ); Thu, 20 Sep 2018 11:40:42 -0400 X-UUID: 8c491479145349289964abb744d3652b-20180920 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1281241049; Thu, 20 Sep 2018 17:57:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 20 Sep 2018 17:57:56 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 20 Sep 2018 17:57:56 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v1 0/3] update Mediatek MT2712 clock Date: Thu, 20 Sep 2018 17:57:24 +0800 Message-ID: <20180920095727.11868-2-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5.2.gbdf23ab In-Reply-To: <20180920095727.11868-1-weiyi.lu@mediatek.com> References: <20180920095727.11868-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: D346A50080EA793DF0670B764E2C66A0B5A194E46A784B18A6278D5681F8C99E2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is based on v4.19-rc1. Basically, it's for the 3rd ECO design change of MT2712. And also add support for switching pll reference source for some MT2712 projects. *** BLURB HERE *** Weiyi Lu (3): dt-bindings: clock: add clock for MT2712 clk: mediatek: update clock driver of MT2712 clk: mediatek: mt2712: add pll reference support drivers/clk/mediatek/clk-mt2712.c | 95 ++++++++++++++++++++++++++-------- include/dt-bindings/clock/mt2712-clk.h | 3 +- 2 files changed, 76 insertions(+), 22 deletions(-) -- 2.12.5.2.gbdf23ab