Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Subject: Re: [PATCH v5 07/18] kvm: arm64: Configure VTCR_EL2 per VM
To:     Auger Eric <eric.auger@redhat.com>,
        linux-arm-kernel@lists.infradead.org
Cc:     kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
        marc.zyngier@arm.com, cdall@kernel.org, pbonzini@redhat.com,
        rkrcmar@redhat.com, will.deacon@arm.com, catalin.marinas@arm.com,
        james.morse@arm.com, dave.martin@arm.com, julien.grall@arm.com,
        linux-kernel@vger.kernel.org
References: <20180917104144.19188-1-suzuki.poulose@arm.com>
 <20180917104144.19188-8-suzuki.poulose@arm.com>
 <3c4d3139-1b8b-12fd-bd41-10a21b86e7b5@redhat.com>
From:   Suzuki K Poulose <suzuki.poulose@arm.com>
Message-ID: <b9d1aa2d-4c9d-5da4-d627-aad7a8e110ee@arm.com>
Date:   Thu, 20 Sep 2018 11:38:51 +0100
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101
 Thunderbird/52.9.1
MIME-Version: 1.0
In-Reply-To: <3c4d3139-1b8b-12fd-bd41-10a21b86e7b5@redhat.com>
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Language: en-US
Content-Transfer-Encoding: quoted-printable
Received-SPF: None (protection.outlook.com: arm.com does not designate
 permitted sender hosts)
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2018 10:38:54.0708
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6994fbaf-173f-4905-b7d2-08d61ee543d5
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d
X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3103
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi Eric,

On 20/09/18 11:21, Auger Eric wrote:
> Hi Suzuki,
>
> On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
>> Add support for setting the VTCR_EL2 per VM, rather than hard
>> coding a value at boot time per CPU. This would allow us to tune
>> the stage2 page table parameters per VM in the later changes.
>>
>> We compute the VTCR fields based on the system wide sanitised
>> feature registers, except for the hardware management of Access
>> Flags (VTCR_EL2.HA). It is fine to run a system with a mix of
>> CPUs that may or may not update the page table Access Flags.
>> Since the bit is RES0 on CPUs that don't support it, the bit
>> should be ignored on them.
>>
>> Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
>> Acked-by: Christoffer Dall <cdall@kernel.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

>> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
>> index b0c07dab5cb3..e0c49377b771 100644
>> --- a/arch/arm64/kvm/reset.c
>> +++ b/arch/arm64/kvm/reset.c
>> @@ -26,6 +26,7 @@
>>
>>   #include <kvm/arm_arch_timer.h>
>>
>> +#include <asm/cpufeature.h>
>>   #include <asm/cputype.h>
>>   #include <asm/ptrace.h>
>>   #include <asm/kvm_arm.h>
>> @@ -134,9 +135,38 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
>>      return kvm_timer_vcpu_reset(vcpu);
>>   }
>>
>> +/*
>> + * Configure the VTCR_EL2 for this VM. The VTCR value is common
>> + * across all the physical CPUs on the system. We use system wide
>> + * sanitised values to fill in different fields, except for Hardware
>> + * Management of Access Flags. HA Flag is set unconditionally on
>> + * all CPUs, as it is safe to run with or without the feature and
>> + * the bit is RES0 on CPUs that don't support it.
>> + */
>>   int kvm_arm_config_vm(struct kvm *kvm, unsigned long type)
>>   {
>> +    u64 vtcr =3D VTCR_EL2_FLAGS;
> #define VTCR_EL2_FLAGS                        (VTCR_EL2_COMMON_BITS | VTC=
R_EL2_TGRAN_FLAGS)
>
> in include/asm/kvm_arm.h
>
> I don't see T0SZ=3D24 encoded there and I don't see it set either in the
> code below? For bisection purpose.

You're right, I am missing it here. I have fixed this up for v6,
with the following hunk.


diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index e0c49377b771..fa897eafc2c9 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -147,6 +147,7 @@ int kvm_arm_config_vm(struct kvm *kvm, unsigned long
type)
  {
        u64 vtcr =3D VTCR_EL2_FLAGS;
        u64 parange;
+       u32 phys_shift;

        if (type)
                return -EINVAL;
@@ -156,6 +157,9 @@ int kvm_arm_config_vm(struct kvm *kvm, unsigned long
type)
                parange =3D ID_AA64MMFR0_PARANGE_MAX;
        vtcr |=3D parange << VTCR_EL2_PS_SHIFT;

+       phys_shift =3D id_aa64mmfr0_parange_to_phys_shift(parange);
+
+       vtcr |=3D VTCR_EL2_T0SZ(phys_shift > 40 ? 40 : phys_shift);
        /*
         * Enable the Hardware Access Flag management, unconditionally
         * on all CPUs. The features is RES0 on CPUs without the support


Thanks
Suzuki
IMPORTANT NOTICE: The contents of this email and any attachments are confid=
ential and may also be privileged. If you are not the intended recipient, p=
lease notify the sender immediately and do not disclose the contents to any=
 other person, use it for any purpose, or store or copy the information in =
any medium. Thank you.