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Message-ID: <5BA394BC.1070804@intel.com>
Date:   Thu, 20 Sep 2018 20:38:20 +0800
From:   Wei Wang <wei.w.wang@intel.com>
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        arei.gonglei@huawei.com
Subject: Re: [PATCH v3 3/5] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to
 the guest
References: <1537437959-8751-1-git-send-email-wei.w.wang@intel.com> <1537437959-8751-4-git-send-email-wei.w.wang@intel.com>
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On 09/20/2018 06:05 PM, Wei Wang wrote:
> Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
> the addresses stored in the LBR stack. Expose those bits to the guest
> when the guest lbr feature is enabled.
>
> Signed-off-by: Like Xu <like.xu@intel.com>
> Signed-off-by: Wei Wang <wei.w.wang@intel.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Andi Kleen <ak@linux.intel.com>
> ---
>   arch/x86/include/asm/perf_event.h | 2 ++
>   arch/x86/kvm/cpuid.c              | 2 +-
>   arch/x86/kvm/vmx.c                | 7 +++++++
>   3 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 84cc8cb..e893a69 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -79,6 +79,8 @@
>   #define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
>   #define ARCH_PERFMON_EVENTS_COUNT			7
>   
> +#define PERF_CAP_MASK_LBR_FMT				0x3f
> +
>   /*
>    * Intel "Architectural Performance Monitoring" CPUID
>    * detection/enumeration details:
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 7bcfa61..3b8a57b 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -365,7 +365,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
>   		F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
>   		0 /* DS-CPL, VMX, SMX, EST */ |
>   		0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
> -		F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
> +		F(FMA) | F(CX16) | 0 /* xTPR Update*/ | F(PDCM) |
>   		F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
>   		F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
>   		0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 533a327..92705b5 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -4134,6 +4134,13 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>   		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
>   			return 1;
>   		/* Otherwise falls through */
> +	case MSR_IA32_PERF_CAPABILITIES:
> +		if (!boot_cpu_has(X86_FEATURE_PDCM))
> +			return 1;
> +		msr_info->data = native_read_msr(MSR_IA32_PERF_CAPABILITIES);
> +		if (vcpu->kvm->arch.guest_lbr_enabled)
> +			msr_info->data &= PERF_CAP_MASK_LBR_FMT;
> +		break;

Sorry about a mistake here. Will move "case MSR_IA32_PERF_CAPABILITIES" 
one step above - above "case TSC_AUX".

Best,
Wei