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[209.132.180.67]) by mx.google.com with ESMTP id o137-v6si28388766pfg.362.2018.09.20.16.32.25; Thu, 20 Sep 2018 16:32:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727643AbeIUFRb (ORCPT + 99 others); Fri, 21 Sep 2018 01:17:31 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:39212 "EHLO smtp2200-217.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725749AbeIUFRb (ORCPT ); Fri, 21 Sep 2018 01:17:31 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.08894381|-1;CH=green;FP=0|0|0|0|0|-1|-1|-1;HT=e01l01425;MF=ren_guo@c-sky.com;NM=1;PH=DS;RN=9;RT=9;SR=0;TI=SMTPD_---.CtbYBbe_1537486265; Received: from localhost(mailfrom:ren_guo@c-sky.com fp:SMTPD_---.CtbYBbe_1537486265) by smtp.aliyun-inc.com(10.147.40.200); Fri, 21 Sep 2018 07:31:05 +0800 Date: Fri, 21 Sep 2018 07:31:04 +0800 From: Guo Ren To: Daniel Lezcano Cc: tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com, arnd@arndb.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, c-sky_gcc_upstream@c-sky.com, green.hu@gmail.com Subject: Re: [PATCH V8 1/2] clocksource: add gx6605s SOC system timer Message-ID: <20180920233103.GA8891@guoren-Inspiron-7460> References: <4d409a1fdecf1c376e8cc6b55308cd3c522047b0.1537412072.git.ren_guo@c-sky.com> <6c31f9b2-d536-1cee-8024-b52eb862fd9d@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6c31f9b2-d536-1cee-8024-b52eb862fd9d@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 20, 2018 at 06:06:19PM +0200, Daniel Lezcano wrote: > On 20/09/2018 10:03, Guo Ren wrote: > > Changelog: > > - Add License and Copyright > > - Use timer-of framework > > - Change name with upstream feedback > > - Use clksource_mmio framework > > > > Signed-off-by: Guo Ren > > --- > > drivers/clocksource/Kconfig | 8 ++ > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/timer-gx6605s.c | 150 ++++++++++++++++++++++++++++++++++++ > > 3 files changed, 159 insertions(+) > > create mode 100644 drivers/clocksource/timer-gx6605s.c > > > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > > index a11f4ba..6d0f18d 100644 > > --- a/drivers/clocksource/Kconfig > > +++ b/drivers/clocksource/Kconfig > > @@ -620,4 +620,12 @@ config RISCV_TIMER > > is accessed via both the SBI and the rdcycle instruction. This is > > required for all RISC-V systems. > > > > +config GX6605S_TIMER > > + bool "Gx6605s SOC system timer driver" > > + depends on CSKY > > + select CLKSRC_MMIO > > + select TIMER_OF > > + help > > + This option enables support for gx6605s SOC's timer. > > + > > endmenu > > Please make the option not visible as default. There are currently two > approaches look at MTK_TIMER and SPRD_TIMER. Em ... (ot sure why COMPILE_TEST?): bool "Gx6605s SOC system timer driver" if COMPILE_TEST Hmm? > > +static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) > > +{ > > + struct clock_event_device *ce = (struct clock_event_device *) dev; > > nit: no cast is needed. Yes, change to: struct clock_event_device *ce = dev; > > +static u64 notrace gx6605s_sched_clock_read(void) > > +{ > > + void __iomem *base; > > + > > + base = timer_of_base(&to) + CLKSRC_OFFSET; > > + > > + return (u64) readl_relaxed(base + TIMER_VALUE); > > nit: extra space after '(u64)' Ok return (u64)readl_relaxed(base + TIMER_VALUE); Best Regards Guo Ren