Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp2455170imm; Mon, 24 Sep 2018 04:48:57 -0700 (PDT) X-Google-Smtp-Source: ACcGV61fZPz3sBP9tAQ3GIb44PyXymDymeo6wJIrVwjVI55f2TzPt1fBIh+zYCpAHbOZTxinVI46 X-Received: by 2002:a63:d946:: with SMTP id e6-v6mr9273194pgj.24.1537789737077; Mon, 24 Sep 2018 04:48:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537789737; cv=none; d=google.com; s=arc-20160816; b=gN5Irrkip1YYUq2V2xiHHgKMQ9Cl6AwQVXVcGFKaAW9soVTIg6ZjVfdjjOlvvLRipx R6LBFwzw2mzxMWoFBcKqtpB6Vfxaic02uXxVjf+FiUSHcR0ic2MZRa8Gzy9P2Wc2EIr2 +3R/L4JDTi66iAtbBp4PTtxsN57uHd6lsOav0Pyjdy8RpJrkum2K7WLqLCz3a9rB4SB3 5z4ABLC2yuK6N9bCEHbZycevcz+Ybm7FtZYkuPYE3quCDdqEuAnW7qI63i4dXVSjAMde x/Kiy0dJ2M5np2Yo6IS5JV8nGHZoZfs/rTqfJNZ28aRxxa6z1NWsBKrixbopLL9x2Cke C0yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:to:from; bh=cYyeZ3CjtwZteYhOAUGc3YRpHkqzN7wmm23Lyx8JP7k=; b=zKTkF4WgRnmwJ6pcP04J37MSzlxQ6O4W1VxXgcNuYHWxJ2yrhtAJRThpZe7RNg6JMj Ol6Uf1S6roFHxX+nVszJBgULRrLBDS6a0cKf8qjAdUg1X3eGLSRKX2YTMV4DYr7XLX4J 5FKsqU0Rexc63+xPwnHZ2UXKrB9u4r4gQwS/4QeBEKINsu75rMLOe8n5PiAG427b1HCN ++9aCKLeA7WVmKn/7S6YuTQ+ObniLz6+jVWjU29BbPVbcxuutS+OFjNEA+3Yn4IV4Jm1 HIBp7TqZFSNN0jMv41o2omNYbdNpaY5Jo96YCtGEWAtnYCQRTra5SROTjoCCqm8bi5a7 pHzQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i23-v6si6543559pgl.230.2018.09.24.04.48.42; Mon, 24 Sep 2018 04:48:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728839AbeIXRia (ORCPT + 99 others); Mon, 24 Sep 2018 13:38:30 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:40001 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728817AbeIXRi2 (ORCPT ); Mon, 24 Sep 2018 13:38:28 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8OBY3Ng010652; Mon, 24 Sep 2018 13:36:38 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2mnb6x2dnk-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 24 Sep 2018 13:36:38 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4E3343D; Mon, 24 Sep 2018 11:36:37 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2D8635650; Mon, 24 Sep 2018 11:36:37 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 24 Sep 2018 13:36:37 +0200 Received: from localhost (10.201.23.97) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 24 Sep 2018 13:36:36 +0200 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , Gustavo Padovan , Maarten Lankhorst , Sean Paul , David Airlie , , Subject: [PATCH v1 0/2] Manage pixel clock & data enable polarities Date: Mon, 24 Sep 2018 13:36:19 +0200 Message-ID: <1537788981-21479-1-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-09-24_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Version 1: - Initial commit This serie contains all patchsets needed for control the pixel clock & data enable polarities by the display controller driver. Yannick Fertré (2): drm: Add missing flags for pixel clock & data enable drm/stm: ltdc: Solve issue on pixel clock & data enable polarity drivers/gpu/drm/drm_modes.c | 19 ++++++++++++++++++- drivers/gpu/drm/stm/ltdc.c | 23 +++++++++++++++++++---- include/uapi/drm/drm_mode.h | 6 ++++++ 3 files changed, 43 insertions(+), 5 deletions(-) -- 2.7.4