Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp2822811imm; Mon, 24 Sep 2018 10:28:03 -0700 (PDT) X-Google-Smtp-Source: ACcGV636xHKo1QopCbbC0Cx1wrxLEZd63RMLnnI2CEVytkRHX5rbwkbpYrjaFhuxb+1c8HHrS65R X-Received: by 2002:a63:a012:: with SMTP id r18-v6mr10468418pge.166.1537810083293; Mon, 24 Sep 2018 10:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537810083; cv=none; d=google.com; s=arc-20160816; b=JhgFq6Gm+DALT/g8RTpiG6tu4ph+359+TeWekR5D2FrsjkGQcLCF4o1JSykZ2E6J/6 Q/5SoztB8z5mdqJhHjBONfa/uxEjPoKGjk7bqrmCtNVYoTaixbkYa4lgMyRob9/SdY4n xSR5tC7p+nDcygNnx4cpKVx8Tcf6nl0ukfJf6VTPbi1CD6c/2JgrsQzLjgcBLDSn9Iwv yqa6+Sq3ho7OH4XHH7oeEabaMyPPqZAeQNzPJanBPEbg1WRAiUATtoudnsv3IJYqLDT9 Q1FWRGw/lStndGu2hTniQCohYE9fGGMhlJQLnhdOjUuCuDkE27QQ5oAURP9Sw1fBMBr6 6rAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date; bh=BAK9Qs9s/YVgWsQOlgyDf0Tq2Q6jLdNFx1fda1Rm7Xw=; b=LdWQ2U8X8cyLaHbZbpDcD62g15FZeZexcR0QMbLsZQu0c5kyQOab+SeNzFhW6muXz4 gV4NekHYrLGyRFYkfL+Appo3YGqu2S2KW0yUPM/RKIas7dKSPPNGvbeLCIsghJ/F/jIc oCb0lIU4I00n9/1QQShbut4RbKx+xDH4Gx6LHgtYD4KOf0ZpmJKjua4s+OhASiGO+KD/ BAeoCyM+Zjv5ybw2MNGy8fRV56ORzHi2MV3F6yckfDCC6mp5ifp+qqlEBBUQRpBimqiQ dH/ZNifTev/gG0oOQvyfOoC1XqJQxe2KpAtd9DUqhOY984CBpChwPkgyUu9R6sxE6S/R i6tA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12-v6si14355332plr.4.2018.09.24.10.27.47; Mon, 24 Sep 2018 10:28:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732905AbeIXX34 (ORCPT + 99 others); Mon, 24 Sep 2018 19:29:56 -0400 Received: from mail.bootlin.com ([62.4.15.54]:46875 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730789AbeIXX34 (ORCPT ); Mon, 24 Sep 2018 19:29:56 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id E5AE620731; Mon, 24 Sep 2018 19:26:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) by mail.bootlin.com (Postfix) with ESMTPSA id A0C9F20379; Mon, 24 Sep 2018 19:26:32 +0200 (CEST) Date: Mon, 24 Sep 2018 19:26:32 +0200 From: Boris Brezillon To: Christophe Kerello Cc: Miquel Raynal , , , , , , , , , , Subject: Re: [PATCH 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver Message-ID: <20180924192632.1d5754da@bbrezillon> In-Reply-To: <6df8455e-2fb2-e65c-a492-fba42a9453f3@st.com> References: <1537199260-7280-1-git-send-email-christophe.kerello@st.com> <1537199260-7280-3-git-send-email-christophe.kerello@st.com> <20180922154819.015dcca7@xps13> <6df8455e-2fb2-e65c-a492-fba42a9453f3@st.com> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 24 Sep 2018 18:36:36 +0200 Christophe Kerello wrote: > >> +static int stm32_fmc2_resume(struct device *dev) > >> +{ > >> + struct stm32_fmc2 *fmc2 = dev_get_drvdata(dev); > >> + int i, ret; > >> + > >> + pinctrl_pm_select_default_state(dev); > >> + > >> + ret = clk_prepare_enable(fmc2->clk); > >> + if (ret) { > >> + dev_err(dev, "can not enable the clock\n"); > >> + return ret; > >> + } > >> + > >> + stm32_fmc2_init(fmc2); > >> + stm32_fmc2_timings_init(fmc2); > >> + stm32_fmc2_setup(fmc2); > >> + > >> + for (i = 0; i < fmc2->ncs; i++) > >> + nand_reset(&fmc2->chip, i); > > > > This means you have one different NAND chip wired on each CS. > > > > We could have two CS wired to the same NAND chip. Calling nand_reset > > twice would be harmless but a lost of time. Actually, you have to call nand_reset() for each CS, otherwise not all dies are reset.