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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 9KcSuYX+wrTOmtSDBQIY+Kh0JcRu29jpll9pA3swjwRUO158GZxDoAyf/be2vSd9HHXeYqaMbe3evgiQ8bYsTYvJlwtnGn46EUXdEsa7rnAU3ng6jGVA3VVb84nCNL7RDgwh7nohLlTUTOwdxSoc3hRa/I0NZzlDnUuydNTSezofzVCD1TPdcnN2XXoEq4D+1U3bVMc7W94S44irab0ZVit9xczaGHnasm5+29aCyi1dVzyLmk4iJDTnjvA+O3aQBMYwFdb6xc9WCWQ2LGksmcHLU+OgPVXTjF5RPuDZ1HYeZ+wK4WllMC13+yrUYpnnsCpdm1rLfx2yBltpfPPSgttdGP3Cc9RgGwRsTH+zVlU= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-ID: <544FC21DF38F2043A71E42A58CABC6B0@namprd08.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf333ea9-c7e4-4429-ae46-08d6230ea4ee X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Sep 2018 17:45:12.6025 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR08MB4776 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yasha, On Thu, Sep 20, 2018 at 08:03:06PM +0300, Yasha Cherikovsky wrote: > MIPSR6 doesn't support unaligned access instructions (lwl, lwr, swl, swr)= . > The MIPS tree has some special cases to avoid these instructions, > and currently the code is testing for CONFIG_CPU_MIPSR6. >=20 > Declare a new Kconfig variable: CONFIG_CPU_HAS_NO_UNALIGNED_LOAD_STORE, > and make CONFIG_CPU_MIPSR6 select it. > And switch all the special cases to test for the new variable. >=20 > Also, the new variable selects CONFIG_GENERIC_CSUM, to use > generic C checksum code (to avoid special assembly code that uses > the unsupported instructions). Thanks for your patch :) I think it would be cleaner to invert this logic & instead have the Kconfig entry indicate when kernel's build target *does* support the [ls]w[lr] instructions. It would be good for the name to be clear that these instructions are what it's about too - "unaligned load store" is a little too vague for my liking. For example one could easily misconstrue it to mean something akin to the inverse of CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS, whereas in the MIPSr6 case many CPUs actually handle unaligned accesses in hardware when using the regular load/store instructions. They don't have the [ls]w[lr] instructions, but they don't need them because they handle unaligned accesses more naturally without needing us to be explicit about them. How about we: - Add a Kconfig option CONFIG_CPU_SUPPORTS_LOAD_STORE_LR, and select it for all existing pre-r6 targets (probably from CONFIG_CPU_*). - Change CONFIG_GENERIC_CSUM to default y if !CONFIG_CPU_SUPPORTS_LOAD_STORE_LR, and drop the selects of it. That would avoid the double-negative ("if we don't not support this") that the #ifndef's currently represent. It would also mean any future architecture/ISA targets beyond MIPSr6 automatically avoid the instructions. Thanks, Paul