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[209.132.180.67]) by mx.google.com with ESMTP id p23-v6si4322397pgl.394.2018.09.25.22.55.06; Tue, 25 Sep 2018 22:55:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b=fazlc9tT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726386AbeIZMGO (ORCPT + 99 others); Wed, 26 Sep 2018 08:06:14 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:42474 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726253AbeIZMGO (ORCPT ); Wed, 26 Sep 2018 08:06:14 -0400 Received: by mail-wr1-f66.google.com with SMTP id b11-v6so9395298wru.9 for ; Tue, 25 Sep 2018 22:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6F//37tKLAYgXDjZTgenOShggxid6AOcFiyV450DGso=; b=fazlc9tTakpyeTjpQB8Y46E0moKh2rkThqLTUduPf0eczWUUFKqXBnBXdVUXnBeSQB U9eQr20gZO3VUPsCcVh5BiJWED1Cls76PmV5wkJU+7SGuhEV+jW5XqrvUqEV7plpE7XU adPKFaPbq2v7shb1IcikY8JSvA8zxd4+tklW3KUZnhNitXMJO0lD2bPnjZAgJsSE8ZV1 xRVd1QfvDYVZSUVQ8BoYcFcOjNhJCZLIni7VAiEOipAX8yVvERnM8G8IMwbu5dj//8+F XSepkFXb/XuWuxoX+PPhPBH+0MjyI+IeeCsjprdDuPCv8HNUTW97h6xOJVAnNFDYZcO+ MQ9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6F//37tKLAYgXDjZTgenOShggxid6AOcFiyV450DGso=; b=EukAeKENRqvaUi93vQhBSKXf6df4XQaXj3lxDz/hd/dMH98ziCAwApwiHr5UouYXea 3kTiZo+AM0Ju4enSTEI+IFtOesfJRNgRbGHqhbW5pjdm+t8nHXsiaQjMFfG6P4FVwmqP FDUVAgEG3FEaI2s5bm+TbRjKmjKOVFUPSawIv751fh4nGwt2mBSjfbR+Zhc48odTcx+T Vi6OgtVuuBkefnqGAH6zyingn/gnndANE9vJGuBpEkPx+BT/Gn/gfFvRYZOhc0i4Dq8K sYowC0J9OMNQVIwsvZBjpwex/hgkrpL4mMyEaJ51C50DT/1kVBVjWlISMpNzwpQqkfmD Ta4A== X-Gm-Message-State: ABuFfogp0JA/Ixj2mrCflw0bbJjjzTDfELVCzTAYEz6yWrhlaZ2+x6lN 508YDjCvUWEpeWSA3zslDoL+X5+q54Pbyth3cX5InQ== X-Received: by 2002:adf:f5ce:: with SMTP id k14-v6mr3587533wrp.59.1537941299876; Tue, 25 Sep 2018 22:54:59 -0700 (PDT) MIME-Version: 1.0 References: <20180910133902.GB21593@infradead.org> <20180910134915.GB30774@infradead.org> <20180910161328.GA13171@infradead.org> <20180910163543.GA13052@infradead.org> <20180917141436.GB2821@infradead.org> In-Reply-To: From: Anup Patel Date: Wed, 26 Sep 2018 11:24:48 +0530 Message-ID: Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver To: Palmer Dabbelt , Christoph Hellwig , Atish Patra , Thomas Gleixner Cc: Jason Cooper , Marc Zyngier , Daniel Lezcano , "linux-kernel@vger.kernel.org List" , Albert Ou , Palmer Dabbelt , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 17, 2018 at 7:58 PM Anup Patel wrote: > > On Mon, Sep 17, 2018 at 7:44 PM Christoph Hellwig wrote: > > > > On Mon, Sep 10, 2018 at 10:08:58PM +0530, Anup Patel wrote: > > > > They could in theory IFF someone actually get the use case through > > > > the riscv privileged spec working group. > > > > > > Their is no point in having each and every possible local interrupts > > > defined by RISC-V spec because some of these will be CPU > > > implementation specific in which case these local interrupts will > > > be described in platform specific DT passed to Linux. > > > > Again, to legally have implementation specific local interrupt types > > you'll first need to convice the spec to change the status for those > > fields from reserved to implementation specific. > > I agree, this needs to be first clarified in RISC-V spec. May be this is > a good topic for discussion in any upcoming RISC-V meetup. > > Until then anyone can try these patches from riscv_intc_v2 branch of > https://github.com/avpatel/linux > I released that CLIC is going to be available for both M-mode and S-mode. Software can choose to use HLIC or CLIC based on it's own preference. If we are going to support both HLIC and CLIC in Linux kernel for per-CPU local interrupts then we should definitely have irqdomain and irqchip for per-CPU local interrupts. The selection between HLIC and CLIC will be based on which driver gets probed via DT. Regards, Anup