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[209.132.180.67]) by mx.google.com with ESMTP id i5-v6si4945493pgg.84.2018.09.26.04.44.21; Wed, 26 Sep 2018 04:44:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728107AbeIZRzW (ORCPT + 99 others); Wed, 26 Sep 2018 13:55:22 -0400 Received: from mail-vs1-f67.google.com ([209.85.217.67]:43636 "EHLO mail-vs1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726593AbeIZRzW (ORCPT ); Wed, 26 Sep 2018 13:55:22 -0400 Received: by mail-vs1-f67.google.com with SMTP id y22-v6so2158747vsj.10; Wed, 26 Sep 2018 04:42:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=N8a2SWnZ9HIWRRCASC+WZvA4QSgGVs+4CVDnVzA5Asg=; b=JF/C/OY0TMP6p7mTfP4mRG7fYtx5512tGPraJ37trv6kmzHnVd7LamgaYCTKcCHwOa C4Q1KXzhcml7oPFB5ryo80CMZVyAZYvhuADjx+l1hjmUpsTZZTY0EwrgLy2VETsMeHRy 9nLjkvfATgQkQQmWesljA5NZn0ajxtJcznMsomaDx23fyHr//HxkGzU1+ZqAUdL1S13C WcbxUs+Rw8bmdfbbG5jSxg0bo7nKRebL2nEmVQwmxmmVza3GLNZZHQ8mNgejjQiS9F+h 9At7p3+AbD/NV1xmL5MVX3YjsuVIgqphAc2SRbVgrzgLOyD9oOCtG9oGp6W6I0Vh/BmE 9c/w== X-Gm-Message-State: ABuFfojCvMDXy5IgCjq1grL4bxopNHhvZ7yFsv62o6s5eocZiaQxanoO /cdkzQH8NMw3QU38SSLlQGvN10fd4rmAiigQ5EI= X-Received: by 2002:a67:f785:: with SMTP id j5-v6mr1336663vso.96.1537962167296; Wed, 26 Sep 2018 04:42:47 -0700 (PDT) MIME-Version: 1.0 References: <20180926091053.21255-1-phil.edworthy@renesas.com> In-Reply-To: <20180926091053.21255-1-phil.edworthy@renesas.com> From: Geert Uytterhoeven Date: Wed, 26 Sep 2018 13:42:35 +0200 Message-ID: Subject: Re: [PATCH v5 0/3] Renesas R9A06G032 PINCTRL Driver To: Phil Edworthy Cc: Laurent Pinchart , Rob Herring , Mark Rutland , Jacopo Mondi , Linus Walleij , Simon Horman , "open list:GPIO SUBSYSTEM" , Linux-Renesas , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Phil, On Wed, Sep 26, 2018 at 11:11 AM Phil Edworthy wrote: > This implements the pinctrl driver for the RZ/N1 family of devices, including > the R9A06G032 (RZ/N1D) device. > > This series was originally written by Michel Pollet whilst at Renesas, and I > have taken over this work. > > Main changes: > v5: > - Address Jacopo's further comments > - Address Geert's comments > > v4: > - Address Jacopo's comments > - Add alternative way to use the pinmux prop. > - Remove mention of gpios. > - Implement pin_config_group_get() > - Fix function to get pin configs, i.e. return -EINVAL when disabled. > > v3: > - Use standard DT props instead of proprietary ones. > - Replace virtual pins used for MDIO muxing with extra funcs. > - Use pinctrl_utils funcs to handle the maps. > - Remove the dbg functions to keep things simple. > - Change the way the functions are defined so it is easy to check > against the hardware numbering. > > v2: > - Change to generic rzn1 family driver, instead of device specific. > - Review comments fixed. > - Fix error handling during probe > > Phil Edworthy (3): > dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation > pinctrl: renesas: Renesas RZ/N1 pinctrl driver > ARM: dts: r9a06g032: Add pinctrl node Thanks, will apply the first two patches to sh-pfc-for-v4.2.0. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds