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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 6WlLwYG065UqNPfya9++3kb4I+awcyU5BSyFzT7fd7ecoS6+FFF9q2IoHoD+Bsup1wf/PhV/y2XeLbZZA5oPEXd3U99TVoLQ20nsw9aUargbPF9hQhlEjaeuKMipmbbxnZG1e0E+OdskHgvYmRh9Yns8Dwr6E/tyTwVnQW0AtB6LvfcorgTFjdfe+HmFTnfThXdp1OR2whVQY1zPw0geMg1s2GViSf+oMt1XDb6oU9mgdNoDAAYKo4hvuHIrMeTowTcoiDP9DkveygEcQSHPoq7UVk85zYLfCnxG2iS3s60Ga4aWtVIvHi9QCUEmA3KjMzT2m6DMNg8HiB7VVIkIcYY4sqrFZc66ULEAnD75Jvk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ecec1ac-9d60-4e64-2fb7-08d623fdf5a8 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Sep 2018 22:18:17.8995 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR08MB5131 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yasha, On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > MIPSR6 CPUs do not support unaligned load/store instructions > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). >=20 > Currently the MIPS tree has some special cases to avoid these > instructions, and the code is testing for !CONFIG_CPU_MIPSR6. >=20 > This patch declares a new Kconfig variable: > CONFIG_CPU_HAS_LOAD_STORE_LR. > This variable indicates that the CPU supports these instructions. >=20 > Then, the patch does the following: > - Carefully selects this option on all CPUs except MIPSR6. > - Switches all the special cases to test for the new variable, > and inverts the logic: > '#ifndef CONFIG_CPU_MIPSR6' turns into > '#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR' > and vice-versa. >=20 > Also, when this variable is NOT selected (e.g. MIPSR6), > CONFIG_GENERIC_CSUM will default to 'y', to compile generic > C checksum code (instead of special assembly code that uses the > unsupported instructions). >=20 > This commit should not affect any existing CPU, and is required > for future Lexra CPU support, that misses these instructions too. >=20 > Signed-off-by: Yasha Cherikovsky > Cc: Ralf Baechle > Cc: Paul Burton > Cc: James Hogan > Cc: linux-mips@linux-mips.org > Cc: linux-kernel@vger.kernel.org > --- > arch/mips/Kconfig | 35 +++++++++++++++++++++++++-- > arch/mips/kernel/unaligned.c | 47 ++++++++++++++++++------------------ > arch/mips/lib/memcpy.S | 10 ++++---- > arch/mips/lib/memset.S | 12 ++++----- > 4 files changed, 67 insertions(+), 37 deletions(-) Thanks - applied to mips-next for 4.20. Paul