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Wed, 26 Sep 2018 15:31:45 -0700 (PDT) Received: from laptop ([37.122.159.87]) by smtp.gmail.com with ESMTPSA id b138-v6sm558595wmb.1.2018.09.26.15.31.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 26 Sep 2018 15:31:45 -0700 (PDT) Message-ID: <7dfadae9a7896db71fabc71bc7c489791be27baa.camel@gmail.com> Subject: Re: [PATCH v2 1/1] MIPS: Add Kconfig variable for CPUs with unaligned load/store instructions From: Yasha Cherikovsky To: Paul Burton Cc: Ralf Baechle , James Hogan , "linux-mips@linux-mips.org" , "linux-kernel@vger.kernel.org" Date: Thu, 27 Sep 2018 01:31:42 +0300 In-Reply-To: <20180926221815.jfh7uv52oyry2gmq@pburton-laptop> References: <20180926111615.6780-1-yasha.che3@gmail.com> <20180926111615.6780-2-yasha.che3@gmail.com> <20180926221815.jfh7uv52oyry2gmq@pburton-laptop> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, On Wed, 2018-09-26 at 22:18 +0000, Paul Burton wrote: > Hi Yasha, > > On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > > MIPSR6 CPUs do not support unaligned load/store instructions > > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > > > Currently the MIPS tree has some special cases to avoid these > > instructions, and the code is testing for !CONFIG_CPU_MIPSR6. > > > > This patch declares a new Kconfig variable: > > CONFIG_CPU_HAS_LOAD_STORE_LR. > > This variable indicates that the CPU supports these instructions. > > > > Then, the patch does the following: > > - Carefully selects this option on all CPUs except MIPSR6. > > - Switches all the special cases to test for the new variable, > > and inverts the logic: > > '#ifndef CONFIG_CPU_MIPSR6' turns into > > '#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR' > > and vice-versa. > > > > Also, when this variable is NOT selected (e.g. MIPSR6), > > CONFIG_GENERIC_CSUM will default to 'y', to compile generic > > C checksum code (instead of special assembly code that uses the > > unsupported instructions). > > > > This commit should not affect any existing CPU, and is required > > for future Lexra CPU support, that misses these instructions too. > > > > Signed-off-by: Yasha Cherikovsky > > Cc: Ralf Baechle > > Cc: Paul Burton > > Cc: James Hogan > > Cc: linux-mips@linux-mips.org > > Cc: linux-kernel@vger.kernel.org > > --- > > arch/mips/Kconfig | 35 +++++++++++++++++++++++++-- > > arch/mips/kernel/unaligned.c | 47 ++++++++++++++++++------------------ > > arch/mips/lib/memcpy.S | 10 ++++---- > > arch/mips/lib/memset.S | 12 ++++----- > > 4 files changed, 67 insertions(+), 37 deletions(-) > > Thanks - applied to mips-next for 4.20. > > Paul Thanks! Yasha