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[209.132.180.67]) by mx.google.com with ESMTP id p1-v6si1636086plb.197.2018.09.27.03.11.48; Thu, 27 Sep 2018 03:12:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727462AbeI0Q2i convert rfc822-to-8bit (ORCPT + 99 others); Thu, 27 Sep 2018 12:28:38 -0400 Received: from mga18.intel.com ([134.134.136.126]:36862 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727154AbeI0Q2i (ORCPT ); Thu, 27 Sep 2018 12:28:38 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2018 03:11:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,310,1534834800"; d="scan'208";a="76650746" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga008.jf.intel.com with ESMTP; 27 Sep 2018 03:10:55 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 27 Sep 2018 03:10:55 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 27 Sep 2018 03:10:55 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.140]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.220]) with mapi id 14.03.0319.002; Thu, 27 Sep 2018 18:10:53 +0800 From: "Wang, Wei W" To: Peter Zijlstra , Andi Kleen CC: "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "Liang, Kan" , "mingo@redhat.com" , "rkrcmar@redhat.com" , "Xu, Like" , "jannh@google.com" , "arei.gonglei@huawei.com" Subject: RE: [PATCH v3 4/5] KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack Thread-Topic: [PATCH v3 4/5] KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack Thread-Index: AQHUUM3pU3aoeAw5SE6eJtMPeYOl0qT4xgeAgAAO9YCACxkHwA== Date: Thu, 27 Sep 2018 10:10:52 +0000 Message-ID: <286AC319A985734F985F78AFA26841F7397FCAF8@shsmsx102.ccr.corp.intel.com> References: <1537437959-8751-1-git-send-email-wei.w.wang@intel.com> <1537437959-8751-5-git-send-email-wei.w.wang@intel.com> <20180920153035.GB10360@tassilo.jf.intel.com> <20180920162407.GA24124@hirez.programming.kicks-ass.net> In-Reply-To: <20180920162407.GA24124@hirez.programming.kicks-ass.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWI3NzM1ZjgtYTQ3Mi00YjViLWJlZDctNDRlZDZiZTI0OWFlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSzU2VTRUQnJtYjJvMFJuQzlnU3RqOEdcL2YydkNQRWpTUW5Seko0cFBISDRhZUZvYlBBbEZpTE5zbWFvdm9nNlYifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday, September 21, 2018 12:24 AM, Peter Zijlstra wrote: > On Thu, Sep 20, 2018 at 08:30:35AM -0700, Andi Kleen wrote: > > > +int intel_pmu_enable_save_guest_lbr(struct kvm_vcpu *vcpu) { > > > + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); > > > + struct perf_event *event; > > > + struct perf_event_attr attr = { > > > + .type = PERF_TYPE_RAW, > > > + .size = sizeof(attr), > > > + .pinned = true, > > > + .exclude_host = true, > > > + .sample_type = PERF_SAMPLE_BRANCH_STACK, > > > + .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK > | > > > + PERF_SAMPLE_BRANCH_USER | > > > + PERF_SAMPLE_BRANCH_KERNEL, > > > > I think that will allocate an extra perfmon counter, right? > > I throught the same too, but I think the exclude_host/guest, whichever is the > right one makes that work for regular counters too. Sorry for being late. I'm not sure if exclude_host/guest would be suitable, for example, if the guest wants to use a perf counter, host will create a perf event with "exclude_host=true" to have the counter not count in host. And "exclude_guest=true" is a flag to the perf core that the counter should not count when the guest runs. What would you think if we add a new flag (e.g. .force_no_counters) to the perf core to indicate not allocating a perf counter? > That code is a wee bit magical and I didn't take the time to reverse engineer > that. It most certainly needs a comment. No problem. I will add more comments in the next version. Best, Wei