Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp589143imm; Fri, 28 Sep 2018 03:40:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV626/Q6xYrD4UiAO9Cr6xsGKkYPI89BF9qsq/A453JWdraQgzzOGc1s0N58fgvSxA8nr13Ek X-Received: by 2002:a65:6398:: with SMTP id h24-v6mr14675181pgv.245.1538131250982; Fri, 28 Sep 2018 03:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538131250; cv=none; d=google.com; s=arc-20160816; b=lOFsPDBU8BmqntEQY77VXLCQYiwII+XKp7bzVRVAGDNhH8AA22aW9sGJ9KbCPcQyf3 EVfOZmBa8VUYxJuwIpyikPPVyyt69RF+C7leWzrRj0zoi1kYb/dOHgoF4JWo1Qdm+3Rz sBxbKKloxFZr6sN8qqRcZbUtvq4ZH2eOKux4s0DBxjTlJSxgpxw8rcgiZtsNoipv2clF 2kLR0IfavBDIDMOgBCRcBYdbyNwDYMJKB0oDcVZHAeu6H/UgxRS5f3IK1V8zswDCT8ng swopdc7FMVIv/GsxXF37I5v8C3dC+dHcy+/TuTLEQ34lgI+X9Rggar/nrpmSABELPm6R FLPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject; bh=iAMUZJii2NhB1ZSqQDwvvd+Ftq8VrGqA5q6t1hVgD6I=; b=M/wvAPy1uTCeNvHwl44dawXUMSW+L/VxcAH3xBJM5MeJt5X1Our4cJkXpQ1baDUmdh +QCnCB3so8B0+HE3z1kdyH45KqcFokJzdMuzuUmKQrQebFnj7M/DBmPz/XvSTuuaYyVF KHVDK9RHy2UeM1QU6JzJ+DuZBOyOKaugtzJxgtIxdloCtbBedneRUm3WlTsTqs9fIEPB G6oZljh7aKG4UJL9xE++Y2PdLaNf/DYg8RLz/WsLvQS1/XgsG7kZxMi5F0MdYieEZQwd 7yi48hXZm6KFXW5vBr4fGHeJX7nG5cmjwYqHIC2j4Di0z69yGnnp8HxdN23Fhwbk2FGl JkZQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u21-v6si4296619pgm.406.2018.09.28.03.40.35; Fri, 28 Sep 2018 03:40:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729384AbeI1RDe (ORCPT + 99 others); Fri, 28 Sep 2018 13:03:34 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:46838 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729008AbeI1RDe (ORCPT ); Fri, 28 Sep 2018 13:03:34 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9ECE7A9; Fri, 28 Sep 2018 03:40:25 -0700 (PDT) Received: from [10.4.13.85] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C6C63F5BD; Fri, 28 Sep 2018 03:40:23 -0700 (PDT) Subject: Re: [PATCH] drivers: irqchip: pdc: setup all edge interrupts as rising edge at GIC To: Lina Iyer , evgreen@chromium.org Cc: bjorn.andersson@linaro.org, rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, andy.gross@linaro.org, sboyd@kernel.org, dianders@chromium.org References: <20180927171810.22968-1-ilina@codeaurora.org> From: Marc Zyngier Organization: ARM Ltd Message-ID: <27d7df0d-4429-dcdd-f527-a33f9385b4e0@arm.com> Date: Fri, 28 Sep 2018 11:40:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180927171810.22968-1-ilina@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/09/18 18:18, Lina Iyer wrote: > The PDC irqchp can convert a falling edge or level low interrupt to a > rising edge or level high interrupt at the GIC. We just need to setup > the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH > as IRQ_TYPE_EDGE_RISING at the GIC. > > Reported-by: Evan Green > Signed-off-by: Lina Iyer > --- > drivers/irqchip/qcom-pdc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c > index b1b47a40a278..faa7d61b9d6c 100644 > --- a/drivers/irqchip/qcom-pdc.c > +++ b/drivers/irqchip/qcom-pdc.c > @@ -124,6 +124,7 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) > break; > case IRQ_TYPE_EDGE_BOTH: > pdc_type = PDC_EDGE_DUAL; > + type = IRQ_TYPE_EDGE_RISING; > break; > case IRQ_TYPE_LEVEL_HIGH: > pdc_type = PDC_LEVEL_HIGH; > Queued for 4.20, with Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") added. Please consider providing these tags in the future. Thanks, M. -- Jazz is not dead. It just smells funny...