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[209.132.180.67]) by mx.google.com with ESMTP id l64-v6si4667316pge.420.2018.09.28.07.58.40; Fri, 28 Sep 2018 07:58:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=VTp8liM+; dkim=pass header.i=@codeaurora.org header.s=default header.b=fgr4on1y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729217AbeI1VVW (ORCPT + 99 others); Fri, 28 Sep 2018 17:21:22 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49364 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726121AbeI1VVW (ORCPT ); Fri, 28 Sep 2018 17:21:22 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8317160B1E; Fri, 28 Sep 2018 14:57:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538146632; bh=ODJUoLgkD36hTImx/WdWBiBCvtXqjKduwsBMT//CJjw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VTp8liM+yUh1KD6rhV5klL52lr5z37tu0ZSbslIYWvAIxydBTtXESwdr47eBNERE6 p9pgzc9QNwZH2OVNn+0gPUhTNnAyFm4vSYt+YpPuuhF5gYBPJefVso5mI6RwwAGUWt CHOwqRpbphr/MS/fgRW+NYJOjU66KrqPWsl6p6Oo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A19216053C; Fri, 28 Sep 2018 14:57:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538146631; bh=ODJUoLgkD36hTImx/WdWBiBCvtXqjKduwsBMT//CJjw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fgr4on1yVzqH1xeHbMDOWp9HHlSIo2n7JW5z/h+ib87o2Uc3MRBpbjPU8xZMjuFo5 OxyX/aPaqXOsVWfZUAqYaNVYM0xhjdPnz9Eusfr09OJLg/QJmvsfHG3ZRBT/4stnX1 2Wkwm2FsbGKQhT4dIhd+O0tmrknknwQHlLwor/x4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A19216053C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Fri, 28 Sep 2018 08:57:10 -0600 From: Lina Iyer To: Marc Zyngier Cc: evgreen@chromium.org, bjorn.andersson@linaro.org, rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, andy.gross@linaro.org, sboyd@kernel.org, dianders@chromium.org Subject: Re: [PATCH] drivers: irqchip: pdc: setup all edge interrupts as rising edge at GIC Message-ID: <20180928145710.GI11144@codeaurora.org> References: <20180927171810.22968-1-ilina@codeaurora.org> <27d7df0d-4429-dcdd-f527-a33f9385b4e0@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <27d7df0d-4429-dcdd-f527-a33f9385b4e0@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 28 2018 at 04:40 -0600, Marc Zyngier wrote: >On 27/09/18 18:18, Lina Iyer wrote: >>The PDC irqchp can convert a falling edge or level low interrupt to a >>rising edge or level high interrupt at the GIC. We just need to setup >>the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH >>as IRQ_TYPE_EDGE_RISING at the GIC. >> >>Reported-by: Evan Green >>Signed-off-by: Lina Iyer >>--- >> drivers/irqchip/qcom-pdc.c | 1 + >> 1 file changed, 1 insertion(+) >> >>diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c >>index b1b47a40a278..faa7d61b9d6c 100644 >>--- a/drivers/irqchip/qcom-pdc.c >>+++ b/drivers/irqchip/qcom-pdc.c >>@@ -124,6 +124,7 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) >> break; >> case IRQ_TYPE_EDGE_BOTH: >> pdc_type = PDC_EDGE_DUAL; >>+ type = IRQ_TYPE_EDGE_RISING; >> break; >> case IRQ_TYPE_LEVEL_HIGH: >> pdc_type = PDC_LEVEL_HIGH; >> > >Queued for 4.20, with > >Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for >QCOM SoCs") > >added. Please consider providing these tags in the future. Thanks Marc. Will do. -- Lina