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[209.132.180.67]) by mx.google.com with ESMTP id b6-v6si1575369pgi.255.2018.09.28.10.34.20; Fri, 28 Sep 2018 10:34:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729588AbeI1X65 (ORCPT + 99 others); Fri, 28 Sep 2018 19:58:57 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55888 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726367AbeI1X65 (ORCPT ); Fri, 28 Sep 2018 19:58:57 -0400 X-UUID: ecae2fd7fcdb4564a63d43912880be73-20180929 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1101918247; Sat, 29 Sep 2018 01:34:02 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 29 Sep 2018 01:34:00 +0800 Received: from [172.21.77.33] (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sat, 29 Sep 2018 01:34:00 +0800 Message-ID: <1538156040.30348.89.camel@mtkswgap22> Subject: Re: [PATCH 1/2] mmc: dt-bindings: add "bus-clk" for MT2712 From: Sean Wang To: Chaotian Jing CC: Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Ryder Lee , Wolfram Sang , , , , , , Date: Sat, 29 Sep 2018 01:34:00 +0800 In-Reply-To: <1538134855-11198-2-git-send-email-chaotian.jing@mediatek.com> References: <1538134855-11198-1-git-send-email-chaotian.jing@mediatek.com> <1538134855-11198-2-git-send-email-chaotian.jing@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-TM-SNTS-SMTP: BF19B54871203A5D54846AEF06A582874388539EF489BF8797DAAB632A65D5E92000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2018-09-28 at 19:40 +0800, Chaotian Jing wrote: > On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together, > or will hang when access MSDC register. > > Signed-off-by: Chaotian Jing > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > index f33467a..182299b 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > @@ -22,6 +22,7 @@ Required properties: > "source" - source clock (required) > "hclk" - HCLK which used for host (required) > "source_cg" - independent source clock gate (required for MT2712) > + "bus_clk" - bus clk used for internal register access(required for MT2712 MSDC0/3) use a full name in the description such as changing "clk" to "clock" and add an extra blank char prior to left parenthesis > - pinctrl-names: should be "default", "state_uhs" > - pinctrl-0: should contain default/high speed pin ctrl > - pinctrl-1: should contain uhs mode pin ctrl