Received: by 2002:ac0:a5a6:0:0:0:0:0 with SMTP id m35-v6csp3674010imm; Mon, 1 Oct 2018 02:34:16 -0700 (PDT) X-Google-Smtp-Source: ACcGV611WDU1fy26ovdzOvYFBSlQ5KRCyqpwKyJ/m9393xfhUyQC7JjzJM5yOSzsR9LYfpherd9j X-Received: by 2002:a17:902:7e49:: with SMTP id a9-v6mr10823202pln.149.1538386456294; Mon, 01 Oct 2018 02:34:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538386456; cv=none; d=google.com; s=arc-20160816; b=mlKYJB9mn9V6rHq1RHyzjdYM0SSdtjr/mTHU7/jhz0rQ52S+hSHKmKcmMjdqUdljQ5 Pxq7UmKk2PhBwxA95Jh6pu3UqcZnghrwSeNKQ+B+A7wNKXzAmHhSHm7g19QbT7fyL661 FJSf2sjGaWaeXJl39F67wANQK1INN+RCJj1zd1fXvGIyponGkK9TkbYYrxzIYvqY0lUT wbP+R2DG76MhxwwmwoltGy+nLqbQG1L8ZfQprnRUuHeW+lB6bWoMAmr8TEwSOikgkcbz UJhvwY+RlUgCoDdNwFZIZeDmmNFf0Msq4Obcbi8U75iCB+csqsrFgeObrZH+zdVkdSkW WKpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :references:in-reply-to:mime-version:dkim-signature; bh=FHz95d/pMGf2H33zSYbM9UM1RBNiXE38wOhfi7Jg5bc=; b=Lk75DBuzV5WnHCCY4W/Qk9b2zpMu4o31L35XcrEXhR5xd2Mi5Yr/0lRfy+bqLDuKuF CI/gWsEJIGXwG9GkO9GlrpIRk4wSu2UG26bPJbEQZC2ZgIFHZZJWbSIV8ku3pGsfhyX+ o5c3/ta4J9ccnVASqgnttYPGwTtAC0b+Z2vn5t4gWDiUIijEZ5QUOM5MVLfjf4fxKavF NttIBlCJ9xRv2p2bddWKJ9MM/pQepFf79cNZUbTHiFG6pdnnv7uKGfY48I6rUBCZev9o 9jCeGycTq7/MYOe9mLASsVhSkwAQupBbjKFckwg3eLY2OCxNy64GxU3XxbWJB9H4srnQ a+6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MMiRlEi/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 14-v6si11300499pgm.488.2018.10.01.02.34.01; Mon, 01 Oct 2018 02:34:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MMiRlEi/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729099AbeJAQIR (ORCPT + 99 others); Mon, 1 Oct 2018 12:08:17 -0400 Received: from mail-it1-f196.google.com ([209.85.166.196]:50822 "EHLO mail-it1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726386AbeJAQIR (ORCPT ); Mon, 1 Oct 2018 12:08:17 -0400 Received: by mail-it1-f196.google.com with SMTP id j81-v6so10353257ite.0 for ; Mon, 01 Oct 2018 02:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FHz95d/pMGf2H33zSYbM9UM1RBNiXE38wOhfi7Jg5bc=; b=MMiRlEi/9tEkV1wKjUujP0yu5jCoUUUAi6Ek1/+tLec5BWpS8InkU6yqeDhGcOeDVF RCNrqlkdRcfz1BKfQDELsw2xBfiCxJOxkmCLmILU7gBBgQI97p6HoSZlB+VlOaWonnrJ 6UD5SuZ23PTkYLnfV04ssl0EHFCyrShwvXVB0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FHz95d/pMGf2H33zSYbM9UM1RBNiXE38wOhfi7Jg5bc=; b=j0b0LPoCtpOBxWF7Xk51KYwX94N5VZY/QnSaf+tFwwL45rDTjvzNlF5oJJj6KbbKgi oEfiQo9kt6/6S48W+Y9+UOCUafDHgTRcYEptZZ9X9CN8vCGnJ7h1Y6OmBT+UAkp7/olb mayCBKjF/kpAU/jV/k2BXWBWS8DoFw6HU93BQ8KQEi4oPkhmUdXWT7Ig35Y8fLoN4QSv KerZs41qBuQsAANwWfomfrY4TQhLg10wbPGh7oOPnXkabRDa2pcX1kSeltVZ72rENkeK lOvX+NMt5vCiunlQiVQRhX58LetL4MBRGQDP0kfeA2eo1XDLXdua8KOMKD6+MopH21r8 7r0A== X-Gm-Message-State: ABuFfojBcmHoiKX5Dx3lhrNi95+TkFyC+umD9/f/htvUa5RmYubP/69Q VcBFuLD7xv8/HHCwN0W9JrMK3P3XfNCSIBDACsLm1Q== X-Received: by 2002:a02:6a6f:: with SMTP id m47-v6mr7654745jaf.121.1538386284647; Mon, 01 Oct 2018 02:31:24 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a02:3941:0:0:0:0:0 with HTTP; Mon, 1 Oct 2018 02:30:44 -0700 (PDT) In-Reply-To: <1537523181-14578-24-git-send-email-ludovic.Barre@st.com> References: <1537523181-14578-1-git-send-email-ludovic.Barre@st.com> <1537523181-14578-24-git-send-email-ludovic.Barre@st.com> From: Ulf Hansson Date: Mon, 1 Oct 2018 11:30:44 +0200 Message-ID: Subject: Re: [PATCH V2 23/27] mmc: mmci: add variant property to request a reset To: Ludovic Barre Cc: Rob Herring , Maxime Coquelin , Alexandre Torgue , Benjamin Gaignard , Gerald Baeza , Loic Pallardy , Linux ARM , Linux Kernel Mailing List , DTML , "linux-mmc@vger.kernel.org" , linux-stm32@st-md-mailman.stormreply.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21 September 2018 at 11:46, Ludovic Barre wrote: > From: Ludovic Barre > > Some variants could require a reset. > STM32 sdmmc variant needs to reset hardware block > during the power cycle procedure (for re-initialization) > > Signed-off-by: Ludovic Barre > --- > Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ > drivers/mmc/host/mmci.c | 9 +++++++++ > drivers/mmc/host/mmci.h | 4 ++++ > 3 files changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt > index 03796cf..e952707 100644 > --- a/Documentation/devicetree/bindings/mmc/mmci.txt > +++ b/Documentation/devicetree/bindings/mmc/mmci.txt > @@ -11,6 +11,8 @@ Required properties: > - compatible : contains "arm,pl18x", "arm,primecell". > - vmmc-supply : phandle to the regulator device tree node, mentioned > as the VCC/VDD supply in the eMMC/SD specs. > +depend of variant: > +- resets : phandle to internal reset line. > This looks like a thing depending on the SoC, rather than on the variant. Therefore, I suggest you move this to be an optional DT property. Also, please move the DT doc update into a separate patch. > Optional properties: > - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c > index b1d5bc5..6b3c33f 100644 > --- a/drivers/mmc/host/mmci.c > +++ b/drivers/mmc/host/mmci.c > @@ -37,6 +37,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -1854,6 +1855,14 @@ static int mmci_probe(struct amba_device *dev, > > dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); > > + if (variant->reset) { > + host->rst = devm_reset_control_get_exclusive(&dev->dev, NULL); As suggested, let's make this optional and not depending on the variant. > + if (IS_ERR(host->rst)) { > + ret = PTR_ERR(host->rst); > + goto clk_disable; > + } > + } > + > /* Get regulators and the supported OCR mask */ > ret = mmc_regulator_get_supply(mmc); > if (ret) > diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h > index e130689..f0fa185 100644 > --- a/drivers/mmc/host/mmci.h > +++ b/drivers/mmc/host/mmci.h > @@ -247,6 +247,7 @@ struct mmci_host; > * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS > * register. > * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register > + * @reset: true if variant has need reset signal. > */ > struct variant_data { > unsigned int clkreg; > @@ -285,6 +286,7 @@ struct variant_data { > bool qcom_dml; > bool reversed_irq_handling; > bool mmcimask1; > + bool reset; > unsigned int irq_pio_mask; > u32 start_err; > u32 opendrain; > @@ -318,6 +320,8 @@ struct mmci_host { > struct clk *clk; > bool singleirq; > > + struct reset_control *rst; > + > spinlock_t lock; > > unsigned int mclk; > -- > 2.7.4 > Kind regards Uffe