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From:   "Kulkarni, Ganapatrao" <Ganapatrao.Kulkarni@cavium.com>
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Subject: [PATCH] arm_pmu: Delete incorrect cache event mapping for some
 armv8_pmuv3 events.
Thread-Topic: [PATCH] arm_pmu: Delete incorrect cache event mapping for some
 armv8_pmuv3 events.
Thread-Index: AQHUWW6YXEMNiP6AC0u/a7CvXSbMkA==
Date:   Mon, 1 Oct 2018 10:07:43 +0000
Message-ID: <20181001100707.16840-1-ganapatrao.kulkarni@cavium.com>
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Perf events L1-dcache-load-misses, L1-dcache-store-misses are mapped to
armv8_pmuv3 (both DT and ACPI) event L1D_CACHE_REFILL. This is incorrect,
since L1D_CACHE_REFILL counts both load and store misses.
Similarly the events L1-dcache-loads, L1-dcache-stores, dTLB-load-misses
and dTLB-loads are wrongly mapped. Hence Deleting all these cache events
from armv8_pmuv3 cache mapping.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 arch/arm64/kernel/perf_event.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.=
c
index 33147aacdafd..6a67ad22d1eb 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -207,17 +207,9 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_=
COUNT_HW_CACHE_MAX]
 						[PERF_COUNT_HW_CACHE_RESULT_MAX] =3D {
 	PERF_CACHE_MAP_ALL_UNSUPPORTED,
=20
-	[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_CACHE,
-	[C(L1D)][C(OP_READ)][C(RESULT_MISS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_CACHE_RE=
FILL,
-	[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_CACHE=
,
-	[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_CACHE_R=
EFILL,
-
 	[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]	=3D ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 	[C(L1I)][C(OP_READ)][C(RESULT_MISS)]	=3D ARMV8_PMUV3_PERFCTR_L1I_CACHE_RE=
FILL,
=20
-	[C(DTLB)][C(OP_READ)][C(RESULT_MISS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_TLB_REF=
ILL,
-	[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)]	=3D ARMV8_PMUV3_PERFCTR_L1D_TLB,
-
 	[C(ITLB)][C(OP_READ)][C(RESULT_MISS)]	=3D ARMV8_PMUV3_PERFCTR_L1I_TLB_REF=
ILL,
 	[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)]	=3D ARMV8_PMUV3_PERFCTR_L1I_TLB,
=20
--=20
2.18.0