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[209.132.180.67]) by mx.google.com with ESMTP id 64-v6si12794988pft.177.2018.10.01.04.54.43; Mon, 01 Oct 2018 04:54:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RdNYCvfc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729252AbeJASby (ORCPT + 99 others); Mon, 1 Oct 2018 14:31:54 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:34452 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729164AbeJASbx (ORCPT ); Mon, 1 Oct 2018 14:31:53 -0400 Received: by mail-io1-f65.google.com with SMTP id k19-v6so3482044iom.1 for ; Mon, 01 Oct 2018 04:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=P/fCu1aTIk+sQtR6OFUAdIW0f90T1WXx0PmJEW47Kuw=; b=RdNYCvfcsoPxHVjWw8KSSasCIVI6mn7kUVsnWz5LGmGbs1F6ojWtx7137myeoJqAAF tgoGViI1zFTN+dEZ/gb5RMAnlKFDG/quRIiruMt74Y1cPAJhPjz+zdsDGdOBNUYgqw/z sRrJDfTtsxFx2Op/ucxszdJndpDLxjwVifgVY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=P/fCu1aTIk+sQtR6OFUAdIW0f90T1WXx0PmJEW47Kuw=; b=HZ9zGXkxLgHaHsoEkJJyBrwMrkqrRy/U0oeRvYpbHw6+KZfjje2oyWJAoLOnE43CFI zfM2H/yJTFLwlfMKLetVfz1o8l2bij9O8bKRcMICX+ZTiHNE++lysYqY2PvArSbTHVvv K4QkQasuORNhJGG0gf8talb2XGYEoKB9UMrCvCyS3nZE92uVanZWhTWtJJk7LUyZ+ItK dJFlhgp6KPSaTh+K3orXsv+yr04Q44+AdMt6uhZ+lykHay0p48CRtobtIzmuUv7mNL1C e77aWcTrkURtY3Q74vUVvV4lbOWjJaj/0xHpumEsUlLEOYXz8np85pnYaHzG2vDdN0+K sVbg== X-Gm-Message-State: ABuFfogOwreLvVL+wo4yQUrzEgjKVfB3j5wmBu5nBm1Damr2r8kAW6Qd +qvJPKgZZMuHdcC1QunVXCraHs35DMfdm0UY13iBaQ== X-Received: by 2002:a6b:4006:: with SMTP id k6-v6mr6132868ioa.277.1538394867585; Mon, 01 Oct 2018 04:54:27 -0700 (PDT) MIME-Version: 1.0 References: <20180921103604.13361-1-ricardo.ribalda@gmail.com> <20180921103604.13361-2-ricardo.ribalda@gmail.com> <153803107307.119890.10052910965015646333@swboyd.mtv.corp.google.com> <3e07cab8-0f3e-7474-8f6d-e6bb16e8f998@codeaurora.org> <5aea282d-6fc9-cd70-cec4-10f28aa819b9@codeaurora.org> In-Reply-To: From: Linus Walleij Date: Mon, 1 Oct 2018 13:54:15 +0200 Message-ID: Subject: Re: [PATCH v2] gpiolib: Show correct direction from the beginning To: Ricardo Ribalda Delgado Cc: timur@kernel.org, jhugo@codeaurora.org, Stephen Boyd , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 28, 2018 at 9:30 PM Ricardo Ribalda Delgado wrote: > How do we proceed from here? Can you fix your driver somehow to > init the valid mask before enabling the gpio? Just include a hunk to the qcom driver reordering this call at the same time. No need to make it separate patches, it need to be tested together anyways. I guess just switch the order of these two: ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); return ret; } ret = msm_gpio_init_valid_mask(chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed to setup irq valid bits\n"); gpiochip_remove(&pctrl->chip); return ret; } > Do we need to make more severe changes on the core? Don't think so. Yours, Linus Walleij