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[209.132.180.67]) by mx.google.com with ESMTP id y24-v6si8033805pgh.36.2018.10.02.03.56.20; Tue, 02 Oct 2018 03:56:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=cirrus.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727362AbeJBRic (ORCPT + 99 others); Tue, 2 Oct 2018 13:38:32 -0400 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:42032 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726244AbeJBRic (ORCPT ); Tue, 2 Oct 2018 13:38:32 -0400 Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w92AsK0d000612; Tue, 2 Oct 2018 05:55:50 -0500 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.cirrus.com Received: from mail3.cirrus.com ([87.246.76.56]) by mx0b-001ae601.pphosted.com with ESMTP id 2mugja1k91-1; Tue, 02 Oct 2018 05:55:49 -0500 Received: from EX17.ad.cirrus.com (ex17.ad.cirrus.com [172.20.9.81]) by mail3.cirrus.com (Postfix) with ESMTP id 3FEAA611C8A7; Tue, 2 Oct 2018 05:57:55 -0500 (CDT) Received: from imbe.wolfsonmicro.main (198.61.95.81) by EX17.ad.cirrus.com (172.20.9.81) with Microsoft SMTP Server id 14.3.408.0; Tue, 2 Oct 2018 11:55:48 +0100 Received: from imbe.wolfsonmicro.main (imbe.wolfsonmicro.main [198.61.95.81]) by imbe.wolfsonmicro.main (8.14.4/8.14.4) with ESMTP id w92Atmqn023479; Tue, 2 Oct 2018 11:55:48 +0100 Date: Tue, 2 Oct 2018 11:55:48 +0100 From: Charles Keepax To: Richard Fitzgerald CC: , , Subject: Re: [PATCH v2 1/2] mfd: madera: Increase wait time for silicon reset Message-ID: <20181002105548.GR1653@imbe.wolfsonmicro.main> References: <20181002104134.29003-1-rf@opensource.cirrus.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20181002104134.29003-1-rf@opensource.cirrus.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=755 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1810020109 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 02, 2018 at 11:41:33AM +0100, Richard Fitzgerald wrote: > Based on latest silicon validation, we should allow at least > 2 milliseconds after DCVDD enable or hard reset before trying > to communicate with the silicon. > > Previously the delay was done as a side-effect of > madera_disable_hard_reset(). As we also need this delay when > enabling DCVDD (with or without hard reset) it is better for it > to be obvious where it happens in every power-up sequence rather > than hidden within another call in some cases. So it has been > moved out into a separate function call. > > Signed-off-by: Richard Fitzgerald > --- Reviewed-by: Charles Keepax Thanks, Charles