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[77.136.152.84]) by smtp.googlemail.com with ESMTPSA id w192-v6sm1943417wmf.33.2018.10.03.05.28.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 05:28:11 -0700 (PDT) Subject: Re: [PATCH] clocksource/drivers/fttmr010: fix invalid interrupt register access To: Tao Ren , Linus Walleij Cc: Thomas Gleixner , Joel Stanley , Andrew Jeffery , Yu Lei , OpenBMC Maillist , "linux-kernel@vger.kernel.org" , "linux-aspeed@lists.ozlabs.org" References: <20181002041437.2493192-1-taoren@fb.com> <3a294c92-bcc6-b42e-b3af-72bc5f607fd9@fb.com> <966C48A9-98F7-4B2B-BCD0-FAF3066C5794@fb.com> From: Daniel Lezcano Message-ID: <6e7703e4-461b-77bf-5c9d-cc9e91c5ef3d@linaro.org> Date: Wed, 3 Oct 2018 14:28:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <966C48A9-98F7-4B2B-BCD0-FAF3066C5794@fb.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/10/2018 09:46, Tao Ren wrote: > On 10/2/18, 11:57 PM, "Linus Walleij" > wrote: > >> My thought is go for (2) and do all changes in one patch :) > > No problem, Linus. One more question: looks like my first patch > 4451d3f59f2a (fix set_next_event handler) is not merged back to > "timers/core". Should I generate this patch on top of the first patch > or on top of the current "timers/core"? Which one would be easier for > you (or Daniel/Thomas)? Sorry I'm pretty new to the community.. Hi Tao, the branch tip:timers/urgent will be merged in tip:/timers/core, so the fixes will be propagated to the master branch. Base your change in top of tip:timers/urgent, the merge will happen soon and both fixes will end up in tip:timers/core. -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog