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[209.132.180.67]) by mx.google.com with ESMTP id p6-v6si1975202pgp.243.2018.10.03.09.57.23; Wed, 03 Oct 2018 09:57:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="RXW/ro75"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727143AbeJCXqW (ORCPT + 99 others); Wed, 3 Oct 2018 19:46:22 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58730 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726842AbeJCXqW (ORCPT ); Wed, 3 Oct 2018 19:46:22 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w93GudO1023821; Wed, 3 Oct 2018 11:56:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1538585799; bh=qScEYM5zHfqp+nd18kabQ7OmGSMnoLM0iLZW25e/4IA=; h=From:To:CC:Subject:Date; b=RXW/ro75udz3BwjysqkegU6xosUeScnlH0mccx06OcvhS4qrhYP1XSw8dVkELVmaq owh3YsgryG+AWPRRRDAsDY5/NptPonWXzBUoHFuA/MzdS8na1RDYQ5YTfea5vE6ovz EKzikkTmpHqrP02ewQiaf+wdcRH/JgWWaPXTTFOg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w93Gudsv010195; Wed, 3 Oct 2018 11:56:39 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 3 Oct 2018 11:56:39 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 3 Oct 2018 11:56:38 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w93GuZMH030968; Wed, 3 Oct 2018 11:56:36 -0500 From: Vignesh R To: Boris Brezillon , Marek Vasut , Rob Herring CC: Brian Norris , Yogesh Gaur , Linux ARM Mailing List , , , , Vignesh R Subject: [PATCH 0/3] spi-nor: Add Octal SPI support Date: Wed, 3 Oct 2018 22:26:00 +0530 Message-ID: <20181003165603.2579-1-vigneshr@ti.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds support for octal mode of mt35x flash. Also, adds support for OSPI version of Cadence QSPI controller. Based on top of patches adding basic support for mt35xu512aba here: https://patchwork.ozlabs.org/cover/971437/ Vignesh R (3): mtd: spi-nor: Add Octal mode support for mt35xu512aba dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller .../devicetree/bindings/mtd/cadence-quadspi.txt | 1 + drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++++++++ drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++++- include/linux/mtd/spi-nor.h | 2 ++ 4 files changed, 22 insertions(+), 1 deletion(-) -- 2.19.0