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[209.132.180.67]) by mx.google.com with ESMTP id u68-v6si2119847pgb.288.2018.10.03.12.48.40; Wed, 03 Oct 2018 12:49:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727225AbeJDCgi (ORCPT + 99 others); Wed, 3 Oct 2018 22:36:38 -0400 Received: from mail.bootlin.com ([62.4.15.54]:48623 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726971AbeJDCgh (ORCPT ); Wed, 3 Oct 2018 22:36:37 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id B731A207C8; Wed, 3 Oct 2018 21:46:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) by mail.bootlin.com (Postfix) with ESMTPSA id 6844B20618; Wed, 3 Oct 2018 21:46:35 +0200 (CEST) Date: Wed, 3 Oct 2018 21:46:33 +0200 From: Boris Brezillon To: Naga Sureshkumar Relli Cc: , , , , , michals@xilinx.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, nagasuresh12@gmail.com Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller Message-ID: <20181003214633.54e93c00@bbrezillon> In-Reply-To: <1537878031-22253-4-git-send-email-naga.sureshkumar.relli@xilinx.com> References: <1537878031-22253-1-git-send-email-naga.sureshkumar.relli@xilinx.com> <1537878031-22253-4-git-send-email-naga.sureshkumar.relli@xilinx.com> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 25 Sep 2018 17:50:31 +0530 Naga Sureshkumar Relli wrote: > +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + const struct nand_op_instr *instr; > + struct anfc_nand_chip *achip = to_anfc_nand(chip); > + struct anfc_nand_controller *nfc = to_anfc(chip->controller); > + unsigned int op_id; > + struct anfc_op nfc_op = {}; > + struct mtd_info *mtd = nand_to_mtd(chip); > + u32 addrcycles; > + > + anfc_parse_instructions(chip, subop, &nfc_op); > + nfc->prog = PROG_PGRD; > + instr = nfc_op.data_instr; > + op_id = nfc_op.data_instr_idx; > + > + addrcycles = achip->raddr_cycles + achip->caddr_cycles; > + > + anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1, Why are the second opcode and the number of address cycles hardcoded. That's simply not future-proof, and I don't want that. Also, I don't understand why you do that, you have all the information you need in subop and you keep guessing some parameters. > + mtd->writesize, addrcycles); > + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col); > + > + return 0; > +}