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From:   Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
To:     Boris Brezillon <boris.brezillon@bootlin.com>
CC:     Vignesh R <vigneshr@ti.com>, Marek Vasut <marek.vasut@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Brian Norris <computersforpeace@gmail.com>,
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        "zhengxunli@mxic.com.tw" <zhengxunli@mxic.com.tw>,
        "masonccyang@mxic.com.tw" <masonccyang@mxic.com.tw>
Subject: RE: [PATCH 1/3] mtd: spi-nor: Add Octal mode support for mt35xu512aba
Thread-Topic: [PATCH 1/3] mtd: spi-nor: Add Octal mode support for
 mt35xu512aba
Thread-Index: AQHUWzpebO9UjE7y3ESdBwkaF5y7X6UOpRKggAAPOICAAAUCUA==
Date:   Thu, 4 Oct 2018 08:47:33 +0000
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Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Thursday, October 4, 2018 1:09 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Cc: Vignesh R <vigneshr@ti.com>; Marek Vasut <marek.vasut@gmail.com>; Rob
> Herring <robh+dt@kernel.org>; Brian Norris <computersforpeace@gmail.com>;
> Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>; linux-
> mtd@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; juliensu@mxic.com.tw; zhengxunli@mxic.com.tw;
> masonccyang@mxic.com.tw
> Subject: Re: [PATCH 1/3] mtd: spi-nor: Add Octal mode support for
> mt35xu512aba
>=20
> +Julien, Zhengxunli and Mason from Macronix
>=20
> Hi Yogesh,
>=20
> On Thu, 4 Oct 2018 06:51:41 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
>=20
> > Hi Vignesh,
> >
> > > -----Original Message-----
> > > From: Vignesh R [mailto:vigneshr@ti.com]
> > > Sent: Wednesday, October 3, 2018 10:26 PM
> > > To: Boris Brezillon <boris.brezillon@bootlin.com>; Marek Vasut
> > > <marek.vasut@gmail.com>; Rob Herring <robh+dt@kernel.org>
> > > Cc: Brian Norris <computersforpeace@gmail.com>; Yogesh Narayan Gaur
> > > <yogeshnarayan.gaur@nxp.com>; Linux ARM Mailing List <linux-arm-
> > > kernel@lists.infradead.org>; linux-mtd@lists.infradead.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Vignesh R
> > > <vigneshr@ti.com>
> > > Subject: [PATCH 1/3] mtd: spi-nor: Add Octal mode support for
> > > mt35xu512aba
> > >
> > > Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines.
> > > It supports read/write over 8 IO lines simulatenously. Add support
> > > for Octal read mode for Micron mt35xu512aba.
> > > Unfortunately, this flash is only complaint to SFDP JESD216B and
> > > does not seem to support newer JESD216C standard that provides auto
> > > detection of Octal mode capabilities and opcodes. Therefore, this
> > > capability is manually added using new SPI_NOR_OCTAL_READ flag.
> > >
> >
> > Thanks for sending the patch-set of adding octal support.
> > If possible, can you share the MT35x datasheet?
> >
> > I also have the patch ready in which I have added support for Read (1-1=
-8 and
> 1-8-8) protocol and Write (1-1-8 and 1-8-8).
> > Also have added support of Octal in driver/spi/spi.c framework.
> >
> > IMO, we would collaborate our patches.
>=20
> Looks like we are of stepping on each others toes here (see this branch [=
1]). I
> guess it's not a problem if we agree on who is working on what.
>=20
> Yogesh, you already sent "spi: add flags for octal I/O data transfer" [3]=
 which is
> only adding the new OCTAL flags but is not patching spi.c and spi-mem.c t=
o take
> those new flags into account. Here is my version of this patch [2] (it's =
still
> missing an update of SPI_MEM_MAX_BUSWIDTH). Let me know what you want
> to do (rework your version to address the problem or take mine).
>=20
I haven't said that I have sent the patches. My patches are ready and neede=
d to be sent for review.
In these patches,  I am adding support for X-X-X protocol for octal support=
 and integrating them with spi  and flash m25p80 interface.

Would send the patches by today evening for review.

Regards
Yogesh Gaur

> Regarding other patches in [2], they're mainly here to add support for X-=
X-X and
> DTR modes and get the m25p80 logic integrated in spi-nor.c so that we can
> really check which NOR operations are supported by the SPI controller.
>=20
> Regards,
>=20
> Boris
>=20
> [1]https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fg=
ith
> ub.com%2Fbbrezillon%2Flinux%2Fcommits%2Fspi-
> nor%2Focto&amp;data=3D02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C3ad
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> oPdNWUWhLM6wZPmrIec%3D&amp;reserved=3D0
> [2]https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fg=
ith
> ub.com%2Fbbrezillon%2Flinux%2Fcommit%2F9854a8fdd23f64e79859fd07a71d4
> a1c57b812f2&amp;data=3D02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C3ad
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> uuWDrl3ggWlA8LRoc%3D&amp;reserved=3D0
> [3]https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fp=
at
> chwork.ozlabs.org%2Fpatch%2F894916%2F&amp;data=3D02%7C01%7Cyogeshnar
> ayan.gaur%40nxp.com%7C3ad4b6f2a4c9470e98f308d629cc8362%7C686ea1d3
> bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636742355682081158&amp;sdata=3Dt
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