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[209.132.180.67]) by mx.google.com with ESMTP id n3-v6si5026543plb.435.2018.10.04.04.14.12; Thu, 04 Oct 2018 04:14:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KCqihe6P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727464AbeJDSFZ (ORCPT + 99 others); Thu, 4 Oct 2018 14:05:25 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:60230 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727183AbeJDSFZ (ORCPT ); Thu, 4 Oct 2018 14:05:25 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id w94BCWNk103604; Thu, 4 Oct 2018 06:12:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1538651552; bh=oan4RXhaeIfz/hST/iWIE+4M9ToQ5PoOrj2b4y0Gexw=; h=From:To:CC:Subject:Date; b=KCqihe6PuxvSkmj1HQF2JNRI00XOZi1Cf0QusrCDQgvB8WE92DZ4QDs9taAS8REUI 5spi89L5qqtaHBb4EKVoLwe0Uf5ZtgHymIg3MTZSnH06NqjGv2OxpIa4cAUu2/Bwwx 3CcLFqdvEJJFVvFHtcl/VYUPz9hlCt5ssuo0AaL8= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w94BCWbJ020023; Thu, 4 Oct 2018 06:12:32 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 4 Oct 2018 06:12:32 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 4 Oct 2018 06:12:32 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w94BCSLa027478; Thu, 4 Oct 2018 06:12:29 -0500 From: Faiz Abbas To: , , CC: , , , , , Subject: [PATCH 0/6] Add Support for MMC/SD in TI's AM65x SOCs Date: Thu, 4 Oct 2018 16:44:45 +0530 Message-ID: <20181004111451.9539-1-faiz_abbas@ti.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following patches add driver support for MMC/SD in TI's AM65x SOCs. There are two controller instances. Both are compatible with eMMC5.1 Host Controller Standard Specification and SD Host Controller Standard Specification 4.10. DT Support patches will be posted separately. Faiz Abbas (6): dt-bindings: phy: am654-mmc-phy: Document new phy bindings phy: am654-mmc-phy: Add Support for MMC PHY on AM654 Devices dt-bindings: mmc: sdhci-of-arasan: Add new compatible for AM654 MMC PHY mmc: sdhci-of-arasan: Add a single data structure to incorporate pdata and soc_ctl_map mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY arm64: defconfig: Enable MMC PHY for AM65xx .../devicetree/bindings/mmc/arasan,sdhci.txt | 1 + .../devicetree/bindings/phy/am654-mmc-phy.txt | 42 +++ arch/arm64/configs/defconfig | 1 + drivers/mmc/host/sdhci-of-arasan.c | 93 +++++- drivers/phy/ti/Kconfig | 7 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-am654-mmc.c | 291 ++++++++++++++++++ 7 files changed, 421 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/am654-mmc-phy.txt create mode 100644 drivers/phy/ti/phy-am654-mmc.c -- 2.18.0