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([2600:1010:b02c:cbf4:5532:1d8f:efe5:8aa]) by smtp.gmail.com with ESMTPSA id o2-v6sm14351380pfj.57.2018.10.04.07.00.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Oct 2018 07:00:46 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (1.0) Subject: Re: [patch 00/11] x86/vdso: Cleanups, simmplifications and CLOCK_TAI support From: Andy Lutomirski X-Mailer: iPhone Mail (16A366) In-Reply-To: <20181004081100.GI19272@hirez.programming.kicks-ass.net> Date: Thu, 4 Oct 2018 07:00:45 -0700 Cc: Vitaly Kuznetsov , Marcelo Tosatti , Andy Lutomirski , Thomas Gleixner , Paolo Bonzini , Radim Krcmar , Wanpeng Li , LKML , X86 ML , Matt Rickard , Stephen Boyd , John Stultz , Florian Weimer , KY Srinivasan , devel@linuxdriverproject.org, Linux Virtualization , Arnd Bergmann , Juergen Gross Content-Transfer-Encoding: quoted-printable Message-Id: References: <20180914125006.349747096@linutronix.de> <87sh1ne64t.fsf@vitty.brq.redhat.com> <20181003190617.GC21381@amt.cnet> <87k1mycfju.fsf@vitty.brq.redhat.com> <20181004081100.GI19272@hirez.programming.kicks-ass.net> To: Peter Zijlstra Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Oct 4, 2018, at 1:11 AM, Peter Zijlstra wrote: >=20 >> On Thu, Oct 04, 2018 at 09:54:45AM +0200, Vitaly Kuznetsov wrote: >> I was hoping to hear this from you :-) If I am to suggest how we can >> move forward I'd propose: >> - Check if pure TSC can be used on SkyLake+ systems (where TSC scaling >> is supported). >> - Check if non-masterclock mode is still needed. E.g. HyperV's TSC page >> clocksource is a single page for the whole VM, not a per-cpu thing. Can >> we think that all the buggy hardware is already gone? >=20 > No, and it is not the hardware you have to worry about (mostly), it is > the frigging PoS firmware people put on it. >=20 > Ever since Nehalem TSC is stable (unless you get to >4 socket systems, > after which it still can be, but bets are off). But even relatively > recent systems fail the TSC sync test because firmware messes it up by > writing to either MSR_TSC or MSR_TSC_ADJUST. >=20 > But the thing is, if the TSC is not synced, you cannot use it for > timekeeping, full stop. So having a single page is fine, it either > contains a mult/shift that is valid, or it indicates TSC is messed up > and you fall back to something else. >=20 > There is no inbetween there. >=20 > For sched_clock we can still use the global page, because the rate will > still be the same for each cpu, it's just offset between CPUs and the > code compensates for that. But if we=E2=80=99re in a KVM guest, then the clock will jump around on the s= ame *vCPU* when the vCPU migrates. But I don=E2=80=99t see how kvmclock helps here, since I don=E2=80=99t think= it=E2=80=99s used for sched_clock.