Received: by 2002:ac0:a582:0:0:0:0:0 with SMTP id m2-v6csp233876imm; Fri, 5 Oct 2018 02:58:53 -0700 (PDT) X-Google-Smtp-Source: ACcGV62M9dzcJYQApbcFBvUC01uBbERH00DLbAmUbwVDKZUJuW5KHUQBYqtri4g5saJ30tGaUJx9 X-Received: by 2002:a17:902:70c3:: with SMTP id l3-v6mr10679444plt.185.1538733533826; Fri, 05 Oct 2018 02:58:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538733533; cv=none; d=google.com; s=arc-20160816; b=OOXpgK7F7jaRqJwD19YMHEQLg+EGx9gjWG7pjzWQiMJcE/qm7cAyyGDfTtIJDk/3uw DabnK7+8ukyNphHPjQr1EZn/uR9Jnh19fiidg9HmGhtZNoBLqBAM6RyAt7moYTvhQdAe njhB5/4LTyUS6i3pOrAEjWYboY8RqWcx4Creqz+tZomEgZZVjCxADY9iZvFTMWV8pOyB 2SBwW9E4kfi9qFK6o9KMHMIrmsKoClm9ykktzY8+W0MqQpFMZK9UE6X24K0py9hzSwtq mG1uSMApMvJtwuAqK8UiIv1MQ6EXJLSZWUm+k/uD165/i679s3dpSsJnn+pAswkbinyo 6DcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date; bh=9u33RDdqiBEBWYxcgdCOXvl757808uqZGc2csMZc41g=; b=RmPwH+5/SziMxl/XatOMiMV9bLfjVCbL1HPIzx/KbGCx8xFnSj1JMpclAXNz9bspnB ayJzGaHUVua4FPX7XFBSN8dOiLBLDaCJdlKq6sBRCuQjDaLehRiuy2kdrAEqItL4V/a+ NsTwXZlGV/G8ME6y/9JQBURSK1Q896O6alW9kf4jAEDv1CS6dHaC6B5NQg2K442AKhcW aC0mheSEEjTHHAYxEepH9YuwWzCR0qYe4gjNLfQGYEoZEl6Q6dPQWfUP4jRJtaLjEfOV I/4G92LTOckO7rgXrtrdcz8ZH5VtCG7nh6uCv7RrumrmpKCeVkyx9EvnM1v29mpoMjN/ nukg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i10-v6si6316416pgb.71.2018.10.05.02.58.37; Fri, 05 Oct 2018 02:58:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727955AbeJEQ4Y (ORCPT + 99 others); Fri, 5 Oct 2018 12:56:24 -0400 Received: from mail.bootlin.com ([62.4.15.54]:38312 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727672AbeJEQ4Y (ORCPT ); Fri, 5 Oct 2018 12:56:24 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 0DCC6207F0; Fri, 5 Oct 2018 11:58:20 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from bbrezillon (AAubervilliers-681-1-28-153.w90-88.abo.wanadoo.fr [90.88.148.153]) by mail.bootlin.com (Postfix) with ESMTPSA id B10DC2074F; Fri, 5 Oct 2018 11:58:09 +0200 (CEST) Date: Fri, 5 Oct 2018 11:58:09 +0200 From: Boris Brezillon To: Cc: , , , , , , , , , , Subject: Re: [PATCH v2 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver Message-ID: <20181005115809.55356782@bbrezillon> In-Reply-To: <1538732520-2800-3-git-send-email-christophe.kerello@st.com> References: <1538732520-2800-1-git-send-email-christophe.kerello@st.com> <1538732520-2800-3-git-send-email-christophe.kerello@st.com> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 5 Oct 2018 11:41:59 +0200 wrote: > +struct stm32_fmc2 { You should inherit from nand_controller even if the nand_chip already embeds a dummy nand controller object. struct nand_controller base; > + struct stm32_fmc2_nand nand; > + struct device *dev; > + void __iomem *io_base; > + void __iomem *data_base[FMC2_MAX_CE]; > + void __iomem *cmd_base[FMC2_MAX_CE]; > + void __iomem *addr_base[FMC2_MAX_CE]; > + phys_addr_t io_phys_addr; > + phys_addr_t data_phys_addr[FMC2_MAX_CE]; > + struct clk *clk; > + > + struct dma_chan *dma_tx_ch; > + struct dma_chan *dma_rx_ch; > + struct dma_chan *dma_ecc_ch; > + struct sg_table dma_data_sg; > + struct sg_table dma_ecc_sg; > + u8 *ecc_buf; > + int dma_ecc_len; > + > + struct completion complete; > + struct completion dma_data_complete; > + struct completion dma_ecc_complete; > + > + u8 cs_assigned; > + int cs_sel; > +};