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Subject: Re: [PATCH 2/3] x86/vdso: Rearrange do_hres() to improve code generation
From:   Andy Lutomirski <luto@amacapital.net>
In-Reply-To: <alpine.DEB.2.21.1810050758370.2876@nanos.tec.linutronix.de>
Date:   Fri, 5 Oct 2018 06:05:19 -0700
Cc:     Andy Lutomirski <luto@kernel.org>, x86@kernel.org,
        LKML <linux-kernel@vger.kernel.org>
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Message-Id: <9CF548E6-37EC-450D-A670-7826BC9F7F08@amacapital.net>
References: <cover.1538689401.git.luto@kernel.org> <99e93a6be59916959ad259482f4cf347e8af9bac.1538689401.git.luto@kernel.org> <alpine.DEB.2.21.1810050758370.2876@nanos.tec.linutronix.de>
To:     Thomas Gleixner <tglx@linutronix.de>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


> On Oct 4, 2018, at 11:00 PM, Thomas Gleixner <tglx@linutronix.de> wrote:
>=20
>> On Thu, 4 Oct 2018, Andy Lutomirski wrote:
>> index 18c8a78d1ec9..419de7552c2f 100644
>> --- a/arch/x86/entry/vdso/vclock_gettime.c
>> +++ b/arch/x86/entry/vdso/vclock_gettime.c
>> @@ -147,10 +147,9 @@ notrace static int do_hres(clockid_t clk, struct tim=
espec *ts)
>>=20
>>    do {
>>        seq =3D gtod_read_begin(gtod);
>> -        ts->tv_sec =3D base->sec;
>> +        cycles =3D vgetcyc(gtod->vclock_mode);
>>        ns =3D base->nsec;
>>        last =3D gtod->cycle_last;
>> -        cycles =3D vgetcyc(gtod->vclock_mode);
>>        if (unlikely((s64)cycles < 0))
>>            return vdso_fallback_gettime(clk, ts);
>>        if (cycles > last)
>> @@ -158,7 +157,7 @@ notrace static int do_hres(clockid_t clk, struct time=
spec *ts)
>>        ns >>=3D gtod->shift;
>>    } while (unlikely(gtod_read_retry(gtod, seq)));
>>=20
>> -    ts->tv_sec +=3D __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
>> +    ts->tv_sec =3D base->sec + __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns)=
;
>=20
> You cannot access base->sec outside of the seqcount protected region. It
> might have been incremented by now and you'll get a time jump by a full
> second.

Duh. Let me try this again.

>=20
> Thanks,
>=20
>    tglx
>=20
>=20