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[209.132.180.67]) by mx.google.com with ESMTP id y30-v6si9398047pgk.13.2018.10.05.15.10.59; Fri, 05 Oct 2018 15:11:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=m5DVC8zt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728341AbeJFFLe (ORCPT + 99 others); Sat, 6 Oct 2018 01:11:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:54912 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726399AbeJFFLe (ORCPT ); Sat, 6 Oct 2018 01:11:34 -0400 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 40C9A21479 for ; Fri, 5 Oct 2018 22:10:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1538777451; bh=OT51Cl0fHtT/qzIbEubgRMTMGIgd1EHPmCzfLKMih4U=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=m5DVC8ztAIZzV5IfVXmBFMnWa/wNJz2q7jWaK8ogulSgZUHJU1OF4vESXPHF4WxF8 TNqa+FZM0nR/XJvPZZooNnIpxvh3ouYw4wjZAPgPnStRxxc89I0bxpcy1YIjgjBk1p znyf4ICB+cIBGbJInSgGing0NJ0jR2RtsdO3+a3U= Received: by mail-wr1-f42.google.com with SMTP id a13-v6so14940378wrt.5 for ; Fri, 05 Oct 2018 15:10:51 -0700 (PDT) X-Gm-Message-State: ABuFfogPhMI1xkqtnlUjUSSI2M2nyV8HE3cXxgTQJHSl/SfXR8A8p9+Q 8liJDGVqEHm4mZrqt+0RCzljTiyQ5GZwsXSVsQJp+A== X-Received: by 2002:adf:82e3:: with SMTP id 90-v6mr9147900wrc.131.1538777449643; Fri, 05 Oct 2018 15:10:49 -0700 (PDT) MIME-Version: 1.0 References: <20181004045948.129142-1-namit@vmware.com> <72B0B378-9515-47C4-8937-9F1E823DD236@amacapital.net> <2A4D16C3-CBE2-490F-8C7A-F5FE437ACC34@vmware.com> In-Reply-To: <2A4D16C3-CBE2-490F-8C7A-F5FE437ACC34@vmware.com> From: Andy Lutomirski Date: Fri, 5 Oct 2018 15:10:38 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC] x86/cpu_entry_area: move part of it back to fixmap To: Nadav Amit Cc: Andrew Lutomirski , Thomas Gleixner , Ingo Molnar , LKML , X86 ML , "Woodhouse, David" , Peter Zijlstra Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 5, 2018 at 3:08 PM Nadav Amit wrote: > > at 10:02 AM, Andy Lutomirski wrote: > > > On Thu, Oct 4, 2018 at 9:31 AM Nadav Amit wrote: > >> at 7:11 AM, Andy Lutomirski wrote: > >> > >>> On Oct 3, 2018, at 9:59 PM, Nadav Amit wrote: > >>> > >>>> This RFC proposes to return part of the entry-area back to the fixma= p to > >>>> improve system-call performance. Currently, since the entry-area is > >>>> mapped far (more than 2GB) away from the kernel text, an indirect br= anch > >>>> is needed to jump from the trampoline into the kernel. Due to Spectr= e > >>>> v2, vulnerable CPUs need to use a retpoline, which introduces an > >>>> overhead of >20 cycles. > >>> > >>> That retpoline is gone in -tip. Can you see how your code stacks up a= gainst -tip? If it=E2=80=99s enough of a win to justify the added complexi= ty, we can try it. > >>> > >>> You can see some pros and cons in the changelog: > >>> > >>> https://na01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgi= t.kernel.org%2Ftip%2Fbf904d2762ee6fc1e4acfcb0772bbfb4a27ad8a6&data=3D02= %7C01%7Cnamit%40vmware.com%7C9996b2dd6f1745dce10b08d62a1b3f3e%7Cb39138ca3ce= e4b4aa4d6cd83d9dd62f0%7C1%7C0%7C636742693864878787&sdata=3DNW0R%2Fv5Oah= ZlTbbNgnFk20sF4Wt1W0MDjtv9g1k%2BWdg%3D&reserved=3D0 > >> > >> Err.. That=E2=80=99s what I get for not following lkml. Very nice disc= ussion. > >> Based on it, I may be able to do an additional micro-optimizations or > >> two. Let me give it a try. > > > > I think you should at least try to benchmark your code against mine, > > since you more or less implemented the alternative I suggested. :) > > That=E2=80=99s what I meant. So I made a couple of tweaksin my implementa= tion to > make as performant as possible. Eventually, there is a 2ns benefit for th= e > trampoline over the unified entry-path on average on my Haswell VM (254ns= vs > 256ns), yet there is some variance (1.2 & 1.5ns stdev correspondingly). > > I don=E2=80=99t know whether such a difference should make one option to = be preferred > over the other. I think it boils down to whether: > > 1. KASLR is needed. Why? KASLR is basically worthless on any existing CPU against attackers who can run local code. > > 2. Can you specialize the code-paths of trampoline/non-trampoline to gain > better performance. For example, by removing the ALTERNATIVE from > SWITCH_TO_KERNEL_CR3 and not reload CR3 on the non-trampoline path, you c= an > avoid an unconditional jmp on machines which are not vulnerable to Meltdo= wn. > > So I can guess what you=E2=80=99d prefer. Let=E2=80=99s see if I=E2=80=99= m right. > 2 ns isn't bad, at least on a non-PTI system. Which, I suppose, means that you should benchmark on AMD :) If the code is reasonably clean, I could get on board.