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[209.132.180.67]) by mx.google.com with ESMTP id k91-v6si14894160pld.187.2018.10.07.02.41.10; Sun, 07 Oct 2018 02:41:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728657AbeJGQrN (ORCPT + 99 others); Sun, 7 Oct 2018 12:47:13 -0400 Received: from mailoutvs42.siol.net ([185.57.226.233]:40252 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728634AbeJGQrN (ORCPT ); Sun, 7 Oct 2018 12:47:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id C28C4520CE6; Sun, 7 Oct 2018 11:40:27 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id rT8AsSmHzPtG; Sun, 7 Oct 2018 11:40:27 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 4175D520CE7; Sun, 7 Oct 2018 11:40:27 +0200 (CEST) Received: from localhost.localdomain (cpe1-8-82.cable.triera.net [213.161.8.82]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id D16E2520CE6; Sun, 7 Oct 2018 11:40:24 +0200 (CEST) From: Jernej Skrabec To: maxime.ripard@bootlin.com, wens@csie.org Cc: robh+dt@kernel.org, sboyd@kernel.org, airlied@linux.ie, architt@codeaurora.org, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH v2 28/29] arm64: dts: allwinner: h6: Add HDMI pipeline Date: Sun, 7 Oct 2018 11:39:04 +0200 Message-Id: <20181007093905.11253-29-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181007093905.11253-1-jernej.skrabec@siol.net> References: <20181007093905.11253-1-jernej.skrabec@siol.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit adds all entries needed for HDMI to function properly. Signed-off-by: Jernej Skrabec [added DE3 bus] Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h6.dtsi index 040828d2e2c0..59dda8f89d23 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -6,8 +6,11 @@ #include #include #include +#include +#include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -86,12 +89,63 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; =20 + de: display-engine { + compatible =3D "allwinner,sun50i-h6-display-engine"; + allwinner,pipelines =3D <&mixer0>; + status =3D "disabled"; + }; + soc { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges; =20 + de3@1000000 { + compatible =3D "allwinner,sun50i-h6-de3", + "allwinner,sun50i-a64-de2"; + reg =3D <0x1000000 0x400000>; + allwinner,sram =3D <&de2_sram 1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible =3D "allwinner,sun50i-h6-de3-clk"; + reg =3D <0x0 0x10000>; + clocks =3D <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names =3D "mod", + "bus"; + resets =3D <&ccu RST_BUS_DE>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mixer0: mixer@100000 { + compatible =3D "allwinner,sun50i-h6-de3-mixer-0"; + reg =3D <0x100000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names =3D "bus", + "mod"; + resets =3D <&display_clocks RST_MIXER0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer0_out: port@1 { + reg =3D <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint =3D <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + }; + syscon: syscon@3000000 { compatible =3D "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control"; @@ -149,6 +203,11 @@ interrupt-controller; #interrupt-cells =3D <3>; =20 + hdmi_pins: hdmi-pins { + pins =3D "PH8", "PH9", "PH10"; + function =3D "hdmi"; + }; + mmc0_pins: mmc0-pins { pins =3D "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -258,6 +317,148 @@ status =3D "disabled"; }; =20 + hdmi: hdmi@6000000 { + compatible =3D "allwinner,sun50i-h6-dw-hdmi"; + reg =3D <0x06000000 0x10000>; + reg-io-width =3D <1>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, + <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; + clock-names =3D "iahb", "isfr", "tmds", "cec", "hdcp", + "hdcp-bus"; + resets =3D <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; + reset-names =3D "ctrl", "hdcp"; + phys =3D <&hdmi_phy>; + phy-names =3D "hdmi-phy"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi_in: port@0 { + reg =3D <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint =3D <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg =3D <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@6010000 { + compatible =3D "allwinner,sun50i-h6-hdmi-phy"; + reg =3D <0x06010000 0x10000>; + clocks =3D <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_HDMI>; + reset-names =3D "phy"; + #phy-cells =3D <0>; + }; + + tcon_top: tcon-top@6510000 { + compatible =3D "allwinner,sun50i-h6-tcon-top"; + reg =3D <0x06510000 0x1000>; + clocks =3D <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>; + clock-names =3D "bus", + "tcon-tv0"; + clock-output-names =3D "tcon-top-tv0"; + resets =3D <&ccu RST_BUS_TCON_TOP>; + reset-names =3D "rst"; + #clock-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_in: port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + tcon_top_mixer0_out_tcon_tv: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv_in_tcon_top_mixer0>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <4>; + + tcon_top_hdmi_in_tcon_tv: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_tv_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg =3D <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint =3D <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv: lcd-controller@6515000 { + compatible =3D "allwinner,sun50i-h6-tcon-tv", + "allwinner,sun8i-r40-tcon-tv"; + reg =3D <0x06515000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_TCON_TV0>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names =3D "ahb", + "tcon-ch1"; + resets =3D <&ccu RST_BUS_TCON_TV0>; + reset-names =3D "lcd"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv_in: port@0 { + reg =3D <0>; + + tcon_tv_in_tcon_top_mixer0: endpoint { + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_tv>; + }; + }; + + tcon_tv_out: port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + tcon_tv_out_tcon_top: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_hdmi_in_tcon_tv>; + }; + }; + }; + }; + r_ccu: clock@7010000 { compatible =3D "allwinner,sun50i-h6-r-ccu"; reg =3D <0x07010000 0x400>; --=20 2.19.0