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[209.132.180.67]) by mx.google.com with ESMTP id o3-v6si15868356pld.281.2018.10.07.14.08.18; Sun, 07 Oct 2018 14:08:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D8F2W07j; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726468AbeJHEMH (ORCPT + 99 others); Mon, 8 Oct 2018 00:12:07 -0400 Received: from mail-it1-f196.google.com ([209.85.166.196]:38403 "EHLO mail-it1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725755AbeJHEMG (ORCPT ); Mon, 8 Oct 2018 00:12:06 -0400 Received: by mail-it1-f196.google.com with SMTP id i76-v6so9379755ita.3 for ; Sun, 07 Oct 2018 14:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PvrFfuoUNDi7qj4rnHFmBEJS1sAyLTIEO2Ozt4HkCec=; b=D8F2W07jedMw0WjejvrDxc6UX/vFkHqNE0+k1dp08L6D5YkBfI7RgbVOeVAklDuMYV BBEef4cs4owIOeavrO7CUAptsG8DOawKlYccV3EBzsLOvZz19CQeKZpPF3o++22soUbp c7gtkKmK7CXJSNgmmjSlITNJcGO0VhAyElSfI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PvrFfuoUNDi7qj4rnHFmBEJS1sAyLTIEO2Ozt4HkCec=; b=h8+iYaM9c4D7fMeDTAy7rkGq/snwuZ0a7GIsVQTjg8h4Q7pu/9XvSKNaUn20fibiS2 arx6qTtjrrqjb/nBcFuWi2yD/8RHSiyq2BLS0NZOyQnLCHWaEgO6/+SW2knsTVyVFVvH zkQEuhLlypH4LiDuhbvu63ELTvLfyBHBIMz0BaPQ+ks4s88bISWb9la32NUYKBzoKja6 GKY8ppDTaskw2XnUJMDD9vYaRB+p8FT81WQsJDvCijx6BS2WgMDH2MeVEKjozZfem6Py VMos0HtU2/VbRSqjwVX25LvNMHL+HBpfJn+se3qcYRP1IGqOIySzvtUF10ma7JdJbTP5 zwWw== X-Gm-Message-State: ABuFfoi38eyoOl15gW0A3pdWXfzDMav6JiN4vkoHu97gHRZbMzwV3/BU 14/dxHqUB87UJXR/OMkThaZarS6TM/rl4baj4ZpQXA== X-Received: by 2002:a02:7789:: with SMTP id g131-v6mr16252652jac.66.1538946214954; Sun, 07 Oct 2018 14:03:34 -0700 (PDT) MIME-Version: 1.0 References: <20181003215350.3550926-1-taoren@fb.com> In-Reply-To: <20181003215350.3550926-1-taoren@fb.com> From: Linus Walleij Date: Sun, 7 Oct 2018 23:03:23 +0200 Message-ID: Subject: Re: [PATCH v2] clocksource/drivers/fttmr010: fix invalid interrupt register access To: taoren@fb.com Cc: Daniel Lezcano , Thomas Gleixner , Joel Stanley , Andrew Jeffery , Yu Lei , "linux-kernel@vger.kernel.org" , linux-aspeed@lists.ozlabs.org, OpenBMC Maillist Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 3, 2018 at 11:54 PM Tao Ren wrote: > TIMER_INTR_MASK register (Base Address of Timer + 0x38) is not designed > for masking interrupts on ast2500 chips, and it's not even listed in > ast2400 datasheet, so it's not safe to access TIMER_INTR_MASK on aspeed > chips. > > Similarly, TIMER_INTR_STATE register (Base Address of Timer + 0x34) is > not interrupt status register on ast2400 and ast2500 chips. Although > there is no side effect to reset the register in fttmr010_common_init(), > it's just misleading to do so. > > Besides, "count_down" is renamed to "is_aspeed" in "fttmr010" structure, > and more comments are added so the code is more readble. > > Signed-off-by: Tao Ren > --- > Changes in v2: > - "count_down" is renamed to "is_aspeed" in "fttmr010" structure. > - more comments are added to make the code more readable. Reviewed-by: Linus Walleij Yours, Linus Walleij