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[209.132.180.67]) by mx.google.com with ESMTP id t192-v6si14792266pgc.485.2018.10.07.20.27.26; Sun, 07 Oct 2018 20:27:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=1U6mfkzF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726762AbeJHKgy (ORCPT + 99 others); Mon, 8 Oct 2018 06:36:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:44998 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726065AbeJHKgy (ORCPT ); Mon, 8 Oct 2018 06:36:54 -0400 Received: from dragon (unknown [45.56.155.247]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 85DAE2077C; Mon, 8 Oct 2018 03:27:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1538969241; bh=kqvechI+pHkfFNCfTkBq/37g5ay98vkSKwva6T3iAbs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=1U6mfkzFeAhKCbBC5AFICHSpU4aO3VxU/fiPfavd3vVlBT5B7sFtDtBQRYtg2pAZG z6S9R71O8k5Xtzq/FIRgTNC1fxff+XWY0Rj1BhX4HBxGSeVDehY/BRw4+5P0yjUkj4 Ddjx/eQOehyjS9kw79Pg7bBuK6Tx+8aFeUG6fbiA= Date: Mon, 8 Oct 2018 11:26:59 +0800 From: Shawn Guo To: Leonard Crestez Cc: Lucas Stach , Lorenzo Pieralisi , Fabio Estevam , Stefan Agner , Marek Vasut , Ulf Hansson , dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de Subject: Re: [PATCH 2/3] PCI: imx: Add multi-pd support Message-ID: <20181008032657.GF3587@dragon> References: <5832128f3b1822839a0f0bbd1cf8313cf586f15f.1538426534.git.leonard.crestez@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5832128f3b1822839a0f0bbd1cf8313cf586f15f.1538426534.git.leonard.crestez@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 01, 2018 at 11:56:17PM +0300, Leonard Crestez wrote: > On some chips the PCIE and PCIE_PHY blocks are in separate power domains > which can be power-gated independently. The driver needs to handle this > by keeping both domain active. > > This is intended for imx6sx where PCIE is in DISPMIX and PCIE_PHY in > it's own domain. Defining the DISPMIX domain requires a way for pcie to > keep it active or it will break when displays are off. > > The power-domains on imx6sx are meant to look like this: > power-domains = <&pd_disp>, <&pd_pci>; > power-domain-names = "pcie", "pcie_phy"; > > Signed-off-by: Leonard Crestez > Reviewed-by: Ulf Hansson > > --- > drivers/pci/controller/dwc/pci-imx6.c | 48 +++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) Bindings document fsl,imx6q-pcie.txt should probably be updated for the new power domain support. Shawn