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Date:   Mon, 8 Oct 2018 17:05:21 +0200
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Jagan Teki <jagan@openedev.com>
Cc:     Jagan Teki <jagan@amarulasolutions.com>,
        Chen-Yu Tsai <wens@csie.org>, Icenowy Zheng <icenowy@aosc.io>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        Vasily Khoruzhick <anarsoul@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will.deacon@arm.com>,
        David Airlie <airlied@linux.ie>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        Michael Trimarchi <michael@amarulasolutions.com>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        devicetree <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [linux-sunxi] Re: [PATCH 06/12] drm/sun4i: sun6i_mipi_dsi: Fix
 VBP size calculation
Message-ID: <20181008150521.mespl2oqkc4j6tjb@flea>
References: <20180927114850.24565-1-jagan@amarulasolutions.com>
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On Mon, Oct 01, 2018 at 01:39:17PM +0530, Jagan Teki wrote:
> On Saturday 29 September 2018 07:23 PM, Maxime Ripard wrote:
> > On Thu, Sep 27, 2018 at 09:50:34PM +0530, Jagan Teki wrote:
> > > On Thu, Sep 27, 2018 at 8:51 PM Maxime Ripard <maxime.ripard@bootlin.=
com> wrote:
> > > >=20
> > > > On Thu, Sep 27, 2018 at 05:18:44PM +0530, Jagan Teki wrote:
> > > > > According to horizontal and vertical timings are defined
> > > > > per the diagram from include/drm/drm_modes.h
> > > > >=20
> > > > > Back porch =3D [hv]total - [hv]sync_end
> > > > >=20
> > > > > So, update SUN6I_DSI_BASIC_SIZE0_VBP calculation as
> > > > > mode->vtotal - mode->vsync_end
> > > > >=20
> > > > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > ---
> > > > >   drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
> > > > >   1 file changed, 2 insertions(+), 2 deletions(-)
> > > > >=20
> > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu=
/drm/sun4i/sun6i_mipi_dsi.c
> > > > > index 1c7e42015645..599284971ab6 100644
> > > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > > > @@ -526,8 +526,8 @@ static void sun6i_dsi_setup_timings(struct su=
n6i_dsi *dsi,
> > > > >        regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
> > > > >                     SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
> > > > >                                               mode->vsync_start) |
> > > > > -                  SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
> > > > > -                                            mode->vdisplay));
> > > > > +                  SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal -
> > > > > +                                            mode->vsync_end));
> > > >=20
> > > > Is it purely theoretical, or did you find some source that back tha=
t?
> > >=20
> > > VSA is done as per that, sync_end - sync start would give sync time.
> >=20
> > That's a different register though.
> >=20
> > > VBP also done in BPI-M64-bsp[1] which results back porch existing code
> > > results fron porch.
> > >=20
> > > [1] https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/linux-sun=
xi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c#L955
> >=20
> > That code does back porch - sync length. Such a calculation doesn't
> > make much sense as is, but you're saying that it results in the front
> > porch. Again, what makes you say that?
>=20
> No what code shows is not a real back porch value used for drm it's panel
> back porch value which is a DTS property in BSP.
> (I made wrong comment on previous mail as front porch, sorry)
>=20
> here is the real code
>=20
> from drivers/video/sunxi/disp2/disp/de/disp_lcd.c
> timmings->ver_sync_time=3D panel_info->lcd_vspw;
> timmings->ver_back_porch=3D panel_info->lcd_vbp-panel_info->lcd_vspw;
>=20
>=20
> u32 vbp =3D panel->lcd_vbp;
> u32 vspw =3D panel->lcd_vspw;
> dsi_dev[sel]->dsi_basic_size0.bits.vbp =3D vbp-vspw;
>=20
> So,
>=20
> dsi_dev[sel]->dsi_basic_size0.bits.vbp =3D panel->lcd_vbp - panel->lcd_vs=
pw;
>=20
> =3D>  timmings->ver_back_porch + panel_info->lcd_vspw - panel_info->lcd_v=
spw
> =3D>  timmings->ver_back_porch
> =3D>  mode->vtotal - mode->end
>=20
> VSA, which a proper value.
>=20
> dsi_dev[sel]->dsi_basic_size0.bits.vsa =3D vspw;
> =3D> panel_info->lcd_vspw;
> =3D> timmings->ver_sync_time
> =3D> mode->vsync_end - mode->vsync_start

Then please write that in your commit log.

Maxime

--=20
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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