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[209.132.180.67]) by mx.google.com with ESMTP id t13-v6si20624188ply.279.2018.10.09.00.33.43; Tue, 09 Oct 2018 00:33:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uy67dr9c; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726569AbeJIOsq (ORCPT + 99 others); Tue, 9 Oct 2018 10:48:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38178 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725855AbeJIOsp (ORCPT ); Tue, 9 Oct 2018 10:48:45 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id w997X40u027885; Tue, 9 Oct 2018 02:33:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539070384; bh=ckoYC9dMIavsd3sNi2wJ9sd7zlN+XfwAfNGdGMDo9yE=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Uy67dr9c3ga7mUYh+86lwd0dpx732aj6cvFKaxA4798G6fpRokALktz2yZo6HcGuf RgGuvE5CVA8mnbqv+HcPVAupc5VWzhMwqlSXUtL1B5knfhi2cwSEZiGMSGdHh5G/U8 CvPImo+/iu+3+dQAdUKCMplY8vh3TfrI+WS+IMAU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w997X2r3026762; Tue, 9 Oct 2018 02:33:04 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 9 Oct 2018 02:33:03 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 9 Oct 2018 02:33:03 -0500 Received: from [172.24.190.215] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w997X0XK008844; Tue, 9 Oct 2018 02:33:01 -0500 Subject: Re: [PATCH 5/6] mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY To: Ulf Hansson CC: Linux Kernel Mailing List , DTML , "linux-mmc@vger.kernel.org" , Kishon , Rob Herring , Catalin Marinas , Adrian Hunter References: <20181004111451.9539-1-faiz_abbas@ti.com> <20181004111451.9539-6-faiz_abbas@ti.com> From: Faiz Abbas Message-ID: Date: Tue, 9 Oct 2018 13:05:19 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Uffe, On Tuesday 09 October 2018 01:00 PM, Ulf Hansson wrote: > On 4 October 2018 at 13:14, Faiz Abbas wrote: >> The current arasan sdhci PHY configuration isn't compatible >> with the PHY on TI's AM654 devices. >> >> Therefore, add a new compatible, AM654 specific quirks >> and a new AM654 specific set_clock function which >> configures the PHY in a sane way. >> >> Signed-off-by: Faiz Abbas >> Signed-off-by: Sekhar Nori > > Applied for next, thanks! > Do I need to repost these in the v2 ? Thanks, Faiz