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Date:   Tue, 9 Oct 2018 21:45:37 -0700
From:   Benson Leung <bleung@google.com>
To:     Enrico Granata <egranata@google.com>
Cc:     Benson Leung <bleung@chromium.org>,
        Olof Johansson <olof@lixom.net>, linux-kernel@vger.kernel.org,
        gwendal@chromium.org, Enrico Granata <egranata@chromium.org>
Subject: Re: [PATCH 2/2] platform/chrome: Add a new interrupt path for
 cros_ec_lpc
Message-ID: <20181010044537.GA147693@decatoncale.mtv.corp.google.com>
References: <20181003184506.149579-1-egranata@google.com>
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Hi Enrico,

On Wed, Oct 03, 2018 at 11:45:06AM -0700, Enrico Granata wrote:
> From: Enrico Granata <egranata@chromium.org>
>=20
> This commit allows cros_ec_lpc to register a direct IRQ instead of relying
> on the ACPI notification chain to receive MKBP events.
>=20
> This change is done in the interest of allowing reduced jitter in the
> communication path between the CrOS EC and the host for receiving sensor
> data.
>=20
> Signed-off-by: Enrico Granata <egranata@chromium.org>

Applied for v4.20. Thanks!

Benson

> ---
>  drivers/platform/chrome/cros_ec_lpc.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
>=20
> diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chr=
ome/cros_ec_lpc.c
> index 31c8b8c49e45..07eea608915e 100644
> --- a/drivers/platform/chrome/cros_ec_lpc.c
> +++ b/drivers/platform/chrome/cros_ec_lpc.c
> @@ -25,6 +25,7 @@
>  #include <linux/dmi.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
> +#include <linux/interrupt.h>
>  #include <linux/mfd/cros_ec.h>
>  #include <linux/mfd/cros_ec_commands.h>
>  #include <linux/mfd/cros_ec_lpc_reg.h>
> @@ -248,7 +249,7 @@ static int cros_ec_lpc_probe(struct platform_device *=
pdev)
>  	acpi_status status;
>  	struct cros_ec_device *ec_dev;
>  	u8 buf[2];
> -	int ret;
> +	int irq, ret;
> =20
>  	if (!devm_request_region(dev, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE,
>  				 dev_name(dev))) {
> @@ -287,6 +288,18 @@ static int cros_ec_lpc_probe(struct platform_device =
*pdev)
>  			   sizeof(struct ec_response_get_protocol_info);
>  	ec_dev->dout_size =3D sizeof(struct ec_host_request);
> =20
> +	/*
> +	 * Some boards do not have an IRQ allotted for cros_ec_lpc,
> +	 * which makes ENXIO an expected (and safe) scenario.
> +	 */
> +	irq =3D platform_get_irq(pdev, 0);
> +	if (irq > 0)
> +		ec_dev->irq =3D irq;
> +	else if (irq !=3D -ENXIO) {
> +		dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq);
> +		return irq;
> +	}
> +
>  	ret =3D cros_ec_register(ec_dev);
>  	if (ret) {
>  		dev_err(dev, "couldn't register ec_dev (%d)\n", ret);
> @@ -294,11 +307,11 @@ static int cros_ec_lpc_probe(struct platform_device=
 *pdev)
>  	}
> =20
>  	/*
> -	 * Connect a notify handler to process MKBP messages if we have a
> -	 * companion ACPI device.
> +	 * If we have a companion ACPI device and no dedicated IRQ
> +	 * connect a notify handler to process MKBP messages.
>  	 */
>  	adev =3D ACPI_COMPANION(dev);
> -	if (adev) {
> +	if (adev && ec_dev->irq <=3D 0) {
>  		status =3D acpi_install_notify_handler(adev->handle,
>  						     ACPI_ALL_NOTIFY,
>  						     cros_ec_lpc_acpi_notify,
> --=20
> 2.19.0.605.g01d371f741-goog
>=20

--=20
Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
bleung@google.com
Chromium OS Project
bleung@chromium.org

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