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[46.91.238.234]) by smtp.gmail.com with ESMTPSA id r8-v6sm25003814wrm.14.2018.10.10.06.49.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Oct 2018 06:49:27 -0700 (PDT) Date: Wed, 10 Oct 2018 15:49:26 +0200 From: Thierry Reding To: Atish Patra Cc: palmer@sifive.com, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, hch@infradead.org Subject: Re: [RFC 1/4] pwm: sifive: Add DT documentation for SiFive PWM Controller. Message-ID: <20181010134926.GD21134@ulmo> References: <1539111085-25502-1-git-send-email-atish.patra@wdc.com> <1539111085-25502-2-git-send-email-atish.patra@wdc.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="YToU2i3Vx8H2dn7O" Content-Disposition: inline In-Reply-To: <1539111085-25502-2-git-send-email-atish.patra@wdc.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --YToU2i3Vx8H2dn7O Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Oct 09, 2018 at 11:51:22AM -0700, Atish Patra wrote: > From: "Wesley W. Terpstra" >=20 > DT documentation for PWM controller added with updated compatible > string. >=20 > Signed-off-by: Wesley W. Terpstra > [Atish: Compatible string update] > Signed-off-by: Atish Patra > --- > .../devicetree/bindings/pwm/pwm-sifive.txt | 32 ++++++++++++++++= ++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt >=20 > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Docum= entation/devicetree/bindings/pwm/pwm-sifive.txt > new file mode 100644 > index 00000000..532b10fc > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt > @@ -0,0 +1,32 @@ > +SiFive PWM controller > + > +Unlike most other PWM controllers, the SiFive PWM controller currently o= nly > +supports one period for all channels in the PWM. This is set globally in= DTS. > +The period also has significant restrictions on the values it can achiev= e, > +which the driver rounds to the nearest achievable frequency. What restrictions are these? If "nearest achievable" is too far off the target period it might be preferable to error out. > +Required properties: > +- compatible: should be one of > + "sifive,fu540-c000-pwm0","sifive,pwm0". What's the '0' in here? A version number? > + PWM controller is HiFive Unleashed specific chip which warrants a > + specific compatible string. The second string is kept for backward > + compatibility until a firmware update with latest compatible string. > +- reg: physical base address and length of the controller's registers > +- clocks: The frequency the controller runs at > +- #pwm-cells: Should be 2. > + The first cell is the PWM channel number > + The second cell is the PWM polarity > +- sifive,approx-period: the driver will get as close to this period as i= t can Given the above comment, maybe "sifive,period"? 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