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[209.132.180.67]) by mx.google.com with ESMTP id q26-v6si21430596pgv.436.2018.10.10.15.54.33; Wed, 10 Oct 2018 15:54:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="nfvi/iX0"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbeJKGSQ (ORCPT + 99 others); Thu, 11 Oct 2018 02:18:16 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:33590 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725988AbeJKGSQ (ORCPT ); Thu, 11 Oct 2018 02:18:16 -0400 Received: by mail-pg1-f194.google.com with SMTP id y18-v6so3204625pge.0; Wed, 10 Oct 2018 15:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VTPfIOwUW3Ndg7aqU9pV85ZbCe2a76m5QYiO25t3jK0=; b=nfvi/iX0qayuFS2PyfJJKomzj1jGqRSdZK81nhLcefloBWqL5KEiQIexfT9g7sD6Qk HPL4ju5fi+4LNDTXr9IWinxXzZmezqlWMQYnDXv0zX9AoYqG5xJLuVaqeQ48jEEpfLeB 1RmK/8AVb1ToVHNZJbQleAgiqKUO/4gXWoYIdqJX/7OGyanEcimbcglulGj3G22TdlG5 Bzk/Ag1Lqa+zHpCPpDj2Mv5V8rtv6l3L1uVarwq5jyPuKKpKKZCsj6FMC5eeFqI4vn/D /G+EA4IDnIiG0+TsHg9lKRdH+LKjC3RiU3AcM8qJIwdF48q7hBKQGpmp965f0eG/CfWs OiIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VTPfIOwUW3Ndg7aqU9pV85ZbCe2a76m5QYiO25t3jK0=; b=FDqr8MuWue+0rGDrjQ0pid9GqYoHL0p4SwlMR87t3XIi6p5ajgJCcCKBzjFj0fpYXf Hj/nlE08YaPvI/ddPqnuTYixPyVfQHvx3nW47mnzn9Y7uAawsFkY4bf9DXzuOoq+Idhc lskXmb9aUUnwW4m0kXV3tPuJXeyJOBU6GjbyNu3c0rlfuTvu0pIjDy/ePZXuzdIWhwcC T/lXR/o67TG5W4NOk3+TZvijqtvElq2ye7nR6pLTMuIohnXCle/HogmfZII9JTMMtjhP QVVnnr0Bpi9Q+z0pnqL4m4llBqHJhmm8S2tbzetSZ2/d4hj0L5HS3Xy+k1AZHx1zMVil d+TQ== X-Gm-Message-State: ABuFfoi/tXLPtwR+DUIZMtyvP53lywphWh2Q6xG8nIlXSjutYAA5fKp6 QGFL6nqsmGITADW9D8GvloEMU81buKvO7JKFuQ4= X-Received: by 2002:a63:bd01:: with SMTP id a1-v6mr14704850pgf.58.1539212038772; Wed, 10 Oct 2018 15:53:58 -0700 (PDT) MIME-Version: 1.0 References: <1539155912-29760-1-git-send-email-wendy.liang@xilinx.com> <1539155912-29760-3-git-send-email-wendy.liang@xilinx.com> <20181010095741.GA14472@e107155-lin> In-Reply-To: <20181010095741.GA14472@e107155-lin> From: Wendy Liang Date: Wed, 10 Oct 2018 15:53:47 -0700 Message-ID: Subject: Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox To: Sudeep Holla Cc: Wendy Liang , Jassi Brar , Michal Simek , Rob Herring , Mark Rutland , Devicetree List , Linux Kernel Mailing List , linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang > > [...] > > > +Optional properties: > > +-------------------- > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep