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[209.132.180.67]) by mx.google.com with ESMTP id z6-v6si27265401pln.287.2018.10.11.04.44.18; Thu, 11 Oct 2018 04:44:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@hmh.eng.br header.s=fm3 header.b=m67xsYwS; dkim=pass header.i=@messagingengine.com header.s=fm1 header.b=Em6kDkTr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727233AbeJKTK2 (ORCPT + 99 others); Thu, 11 Oct 2018 15:10:28 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:34915 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726071AbeJKTK2 (ORCPT ); Thu, 11 Oct 2018 15:10:28 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id BD4D121E32; Thu, 11 Oct 2018 07:43:35 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Thu, 11 Oct 2018 07:43:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hmh.eng.br; h= date:from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=fm3; bh=T70wiWg2mYWbvU+CAeYThzMbO59 iNJ3wEEYkJi44Q4Y=; b=m67xsYwSwotO/hxV+DedAlWz7hhLqREbmIyj1v01qmo s2toeVCek9/1SNKXhvQpQqVjzIOsoowPmELqHBQTxNFWad42WTdgqYWGOTwTjYJi 4JqJ+olwAgyYkmzV/ANhOLe/3hKWtXd4PmNJGB8sFONK2RIrBVytF/zt5dIhUxsP CHpbk7bpAVIKweVChVVHi/3S3sMoZRVCrLO5jHLWFnWVsHaGvdSH+j0TtWAAaY1p WFBrdrYTVDyu2nmpboT8XojbzoV8B1nSFfOlzseqi6QsY/ojxMYf3627ByUUyWtz +X6ISG2aG8cwzQEh8o5NyBKJ0NC13Ej6ZzOzZiuhluw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=T70wiW g2mYWbvU+CAeYThzMbO59iNJ3wEEYkJi44Q4Y=; b=Em6kDkTrflFqHpfNMJPQWy +h3LB7R7aYA9U0+7ISincHvUS1w67CyjP/5XgCL+IE48vlhde4NsM6TsIvjQfDew elhb9K/WNkgkEMq4LfuoJegqroMpfgl3mO1Fg/Tx/xNhmiNeFvozuqtdaGxHycb/ m5WqcWwf7OH6IyH4iLoQY/iFctXKK594N9LRwjs7v3o9FQtUbNfc2Fv3R+D3IeIj q68XymepfOmjsavr4d8gRlIrO2t6B5Deazl0EG41ezRoYu3+tJjB90RmuOyBWdax vCEDZyXAiHNaHSLiOFP5DOQ9Eak++yuu3yR5cFmjJvVatFgFaI+NPr4ldbjJvahw == X-ME-Sender: X-ME-Proxy: Received: from khazad-dum.debian.net (unknown [201.53.245.99]) by mail.messagingengine.com (Postfix) with ESMTPA id 9206A102EA; Thu, 11 Oct 2018 07:43:32 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by localhost.khazad-dum.debian.net (Postfix) with ESMTP id 5F20D3403991; Thu, 11 Oct 2018 08:43:29 -0300 (-03) X-Virus-Scanned: Debian amavisd-new at khazad-dum.debian.net Received: from khazad-dum.debian.net ([127.0.0.1]) by localhost (khazad-dum2.khazad-dum.debian.net [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 2ni_b-KRft9Y; Thu, 11 Oct 2018 08:43:28 -0300 (-03) Received: by khazad-dum.debian.net (Postfix, from userid 1000) id EA81E3403990; Thu, 11 Oct 2018 08:43:27 -0300 (-03) Date: Thu, 11 Oct 2018 08:43:27 -0300 From: Henrique de Moraes Holschuh To: Andi Kleen Cc: peterz@infradead.org, x86@kernel.org, eranian@google.com, kan.liang@intel.com, linux-kernel@vger.kernel.org, Andi Kleen Subject: Re: [PATCH v2 1/2] x86/cpufeature: Add facility to match microcode revisions Message-ID: <20181011114327.oo3at77hxucpfaon@khazad-dum.debian.net> References: <20181010162608.23899-1-andi@firstfloor.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181010162608.23899-1-andi@firstfloor.org> X-GPG-Fingerprint1: 4096R/0x0BD9E81139CB4807: C467 A717 507B BAFE D3C1 6092 0BD9 E811 39CB 4807 User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 10 Oct 2018, Andi Kleen wrote: > v2: > Remove all CPU match, only check boot cpu IMHO, since it looks like a v3 will be necessary anyway, it could benefit from a comment reminding people about how to use it on older systems where "mixed CPU stepping" configurations were common. This is *not* a relevant limitation, and it is easy enough to handle. But people writing quirks for very old Intel Xeon CPUs *today* (unlikely as that might be) might well forget the mixed-stepping gotcha... Note that while mixed-stepping SMP configurations are *not* current practice, they *were* reasonably common practice more than a decade ago, officially supported both by Intel (there are Intel documents detailing the valid stepping combinations) and the server vendors. Suggestion below. > +/* > + * Match specific microcodes > + * > + * vendor/family/model/stepping must be all set. > + * min_ucode is optional and can be 0. * only checks against the boot cpu. When mixed-stepping configs are valid for a CPU model, add a quirk for every valid stepping and do the fine-tuning in the quirk handler. -- Henrique Holschuh