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From:   Paul Burton <paul.burton@mips.com>
To:     "Maciej W. Rozycki" <macro@linux-mips.org>
CC:     Ralf Baechle <ralf@linux-mips.org>,
        "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/2] MIPS: memset: Fix `noreorder' issues
Thread-Topic: [PATCH 0/2] MIPS: memset: Fix `noreorder' issues
Thread-Index: AQHUWkYO0A6BEjhkeE26NbT1An8AaqUaTG0A
Date:   Thu, 11 Oct 2018 16:36:01 +0000
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Hi Maciej,

On Tue, Oct 02, 2018 at 12:50:00PM +0100, Maciej W. Rozycki wrote:
>  A recent change broke CPU_DADDI_WORKAROUNDS support in memset.S, due to =
a=20
> delay-slot instruction expanding to multiple hardware operations for the=
=20
> affected configurations.
>=20
>  The underlying cause is the excessive use of the `noreorder' assembly=20
> mode, while it is only needed in couple of places where either there is a=
=20
> data dependency between a branch and its delay slot instruction, or there=
=20
> is a section switch involved that would prevent automatic delay slot=20
> scheduling.
>=20
>  These changes address both problems and for clarity, not to mix multiple=
=20
> conceptually separate changes and to make backporting easier I made them =
a=20
> small patch series.  See individual change descriptions for details.
>=20
>  This has been build-time and run-time verified with 32-bit and 64-bit=20
> DECstation configurations, build-time verified with big-endian and=20
> little-endian 64-bit SWARM configurations.  Build-time verification was=20
> made by running `objdump -d arch/mips/lib/memset.o' with a pristine and=20
> and a patched build to make sure there has been no change in machine code=
=20
> generation, except for the delay-slot multiple instruction with the 64-bi=
t=20
> CPU_DADDI_WORKAROUNDS DECstation configuration.

Thanks - I applied patch 1 to mips-fixes & it's already been merged to
master.

Patch 2 applied to mips-next for 4.20.

Paul