Received: by 2002:ac0:a582:0:0:0:0:0 with SMTP id m2-v6csp2627868imm; Thu, 11 Oct 2018 13:26:15 -0700 (PDT) X-Google-Smtp-Source: ACcGV61ivrsvo5BDWmBXHj7DYjT7rMg5yySOV8eEacwkMUlUs6X6zcN0Q4GCfGl9qAHLqU3Jv9mg X-Received: by 2002:a63:c84c:: with SMTP id l12-v6mr2703310pgi.77.1539289575236; Thu, 11 Oct 2018 13:26:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539289575; cv=none; d=google.com; s=arc-20160816; b=nAWlhBvEH7g/hco+go1mym+zUAHzFhpA+GjQe4Xi3L2TTTUld85TLhC8FOCsQj+Zim P2MP95YeYJcolV3kkVvvVsz7MrN5fgqaKa7iIXZxZtAfqFZR+js1ZcfRdoRaCRORz4Kk YKxRBHqW3Q8yftt+pHhPznfnaLbDpFXuP9NJ91TC2tDHViHdgUPt4G3/kE0jqjcb1eE4 sqIeulg3WAJy7Gam3amM/aaHY4oDZt4cj96si68BKf6JiJd2UBEYoaaAik9yPvu2VvlI 32fvTQp6SFi8sWDPnsaHF20GVK6YtxlkIavqzCaQNsjpTwLMv881EyWPMiIpn8LMfAi4 l92g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date; bh=+jFmwmezauwa4qUDhmpqcNYLcPnLBqooIBCk6FoZ11Q=; b=c8PPe/W/dkrU+xFiaAGOAN9cnswne2yWisg195rKpIll2dpmoc2EtydYfrNVMXogMB 6g8+Jc2fcFMeW2RUZTZX6H8EbNGqFd9x6NECD53hmWnoLBrqclhXN2Pp5f4NTQlY3SqF +dFaJCDQzOx7XP8JXKkr5Y8S4qGbGERCsy5zVWktiz687Oernrql9H5etxw96tBH2duU d37lRW8myNn6hCR1wCzGS+PXUAoi2TNj4dU9phlAg0+BRnKGiwYsTGmq3uaCwALgQFA7 mpCItYj18LAHXqfP/DlOCkWxJvxXnWfbVLxXKTqFJ71O5oMUOStPmGUkye2MJFVi1jpN VJnA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n135-v6si32555222pfd.38.2018.10.11.13.25.59; Thu, 11 Oct 2018 13:26:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726376AbeJLDyb (ORCPT + 99 others); Thu, 11 Oct 2018 23:54:31 -0400 Received: from www.llwyncelyn.cymru ([82.70.14.225]:45406 "EHLO fuzix.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726168AbeJLDya (ORCPT ); Thu, 11 Oct 2018 23:54:30 -0400 Received: from alans-desktop (82-70-14-226.dsl.in-addr.zen.co.uk [82.70.14.226]) by fuzix.org (8.15.2/8.15.2) with ESMTP id w9BKP41V003858; Thu, 11 Oct 2018 21:25:04 +0100 Date: Thu, 11 Oct 2018 21:25:04 +0100 From: Alan Cox To: Andy Lutomirski Cc: Kristen Carlson Accardi , Kernel Hardening , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , X86 ML , LKML Subject: Re: [PATCH] x86: entry: flush the cache if syscall error Message-ID: <20181011212504.012c3ece@alans-desktop> In-Reply-To: References: <20181011185458.10186-1-kristen@linux.intel.com> Organization: Intel Corporation X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Ugh. > > What exactly is this trying to protect against? And how many cycles Most attacks by speculation rely upon leaving footprints in the L1 cache. They also almost inevitably resolve non speculatively to errors. If you look through all the 'yet another potential spectre case' patches people have found they would have been rendered close to useless by this change. It's a way to deal with the ones we don't know about, all the ones the tools won't find and it has pretty much zero cost (If you are bored strace an entire days desktop session, bang it through a script or two to extract the number of triggerig error returns and do the maths...) > should we expect L1D_FLUSH to take? More to the point you pretty much never trigger it. Errors are not the normal path in real code. The original version of this code emptied the L1 the hard way - and even then it was in the noise for real workloads we tried. You can argue that the other thread could be some evil task that deliberately triggers flushes, but it can already thrash the L1 on processors that share L1 between threads using perfectly normal memory instructions. Alan